Multi-Format Driver Interface With Current-Loop Output Loading
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Solution Overview
Problem
Existing multi-format driver interfaces for high-speed data communications, such as LVPECL, LVDS, and HCSL, face challenges in power consumption and signal integrity due to double-loading of transistors, which degrades rise and fall times and increases noise performance, especially in high-speed applications.
Innovation Solution
A combined multi-format driver interface is developed, where the LVPECL driver is implemented as a current loop driver, eliminating the need for source followers, and transistor sizing is optimized to reduce power consumption and improve signal integrity, allowing for efficient handling of different signaling formats with a common driver configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate output driver stages are used for each signal format (LVDS, HCSL, LVPECL), then each format can be driven independently, but the transistor pairs are double-loaded which degrades rise and fall times and increases noise
Solution Approach 1:
The patent segments the driver architecture by introducing a pre-driver stage that separates the CML input from the full-swing output drivers. This pre-driver converts the small-swing CML signal to full-swing signals that can independently drive each output format without mutual loading effects, thus improving rise and fall times while maintaining signal integrity.
Solution Approach 2:
The patent introduces an intermediary pre-driver stage between the CML input and the output drivers. This intermediary converts the input signal to a form that can efficiently drive multiple output formats without the transistors being double-loaded, thereby resolving the contradiction between signal integrity and switching speed.
2Speed
If transistor size is increased to improve transconductance and reduce rise/fall time, then speed performance improves, but die area increases
Solution Approach 1:
By segmenting the driver into pre-driver and output driver stages, the patent allows the output drivers to be optimized for low area while the pre-driver handles the transconductance requirements. This segmentation enables achieving fast rise and fall times without proportionally increasing the total die area.
Solution Approach 2:
The patent changes the operating parameters by converting the CML small-swing signal to full-swing signals in the pre-driver stage. This parameter change allows the output drivers to operate more efficiently with smaller transistor sizes, reducing die area while maintaining fast switching performance.
3Speed
If biasing current is increased to improve transconductance and reduce rise/fall time, then speed performance improves, but power consumption increases
Solution Approach 1:
The patent segments the current consumption across two stages: the pre-driver consumes moderate current to generate full-swing signals, while the output drivers consume less current due to the improved signal levels. This segmentation reduces total power consumption compared to a single-stage design that would require high biasing current throughout.
Solution Approach 2:
The pre-driver performs preliminary conversion of the CML signal to full-swing signals before they reach the output drivers. This preliminary action reduces the burden on the output drivers, allowing them to operate with lower biasing current while still achieving fast rise and fall times, thus reducing overall power consumption.
4Adaptability or versatility
If multiple transistor pairs are used to drive different formats, then format versatility is achieved, but device complexity increases
Solution Approach 1:
The patent implements universality by designing output driver stages that can be configured to drive multiple signal formats (LVDS, HCSL, LVPECL) through selective enabling. The common full-swing signal from the pre-driver can drive any of these formats, reducing the need for completely separate driver circuits for each format and simplifying the overall architecture.
Solution Approach 2:
The patent introduces dynamic control through format selection logic that enables or disables specific output drivers based on the required signal format. This dynamic configuration allows a single multi-format driver interface to adapt to different formats without requiring fixed, complex dedicated circuits for each format, thereby reducing overall device complexity.
Data Source
AI summary
A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.