Multi-Frame Error Correction Coding for Burst Error Handling

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Solution Overview

Problem

Existing error correction coding apparatuses in lightwave transmission systems are limited in their ability to correct burst errors due to restrictions imposed by the size of FEC frames, which restricts their capability in this regard.

Innovation Solution

The apparatus includes a first coding unit for generating error correcting code words and a rearranging unit that rearranges elements of the code words across multiple frames, allowing coding processing without size restrictions, thereby enhancing burst error correction capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If coding processing is performed in units of FEC frames with fixed size, then the coding structure is simple and manageable, but the capability of correcting burst errors is restricted by the frame size

Engineering Contradiction:
Improveburst error correction capabilityVSAvoidcoding structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the error correction process into two distinct stages: first, FEC frame-based coding with RS codes provides basic error correction, and second, a block interleaver divides and redistributes data blocks across multiple frames to address burst errors. This segmentation allows each stage to specialize in different error types without overwhelming complexity in a single system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a nested structure where block interleaving is embedded within the FEC frame structure. The block interleaver operates on data blocks that are contained within and span across multiple FEC frames, creating a hierarchical error correction system where the inner FEC coding is protected by the outer block interleaving layer, enhancing burst error correction while maintaining manageable complexity at each level.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the size of FEC frames is increased to improve burst error correction, then more errors can be corrected, but the processing time and system complexity increase

Engineering Contradiction:
Improveburst error correction capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Instead of using large FEC frames, the patent segments the error correction function across multiple standard-sized frames using block interleaving. Data is divided into blocks that are distributed across N FEC frames, allowing the system to achieve equivalent or superior burst error correction to large frames while maintaining the faster processing characteristics of standard frame sizes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The block interleaver performs preliminary rearrangement of data blocks before transmission across multiple frames. This preliminary action distributes consecutive data blocks across different frames in a predetermined pattern, so that when burst errors occur, they affect only portions of different blocks rather than entire large frames, enabling efficient correction without increasing frame processing time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7895498B2Apparatuses and method for error correction coding and error correction decoding
Publication Date: 2011.02.22 MITSUBISHI ELECTRIC CORP
  • US7895498B2 patent drawing
  • US7895498B2 patent drawing
  • US7895498B2 patent drawing

AI summary

An error correction coding apparatus includes a first coding unit for coding a sequence data to be coded which includes information source data for each frame to generate an error correcting code word sequence including a parity sequences, and a first rearranging unit for rearranging elements of the error correcting code word sequences of a plurality of frames generated by the first coding unit. The first rearranging unit rearranges elements of the parity sequences included in the error correcting code word sequences. The first rearranging unit also rearranges elements of the error correcting code word sequences other than the parity sequences, within the error correcting code word sequences other than the parity sequences.