Multigate Source-Drain Engineering With Airgaps for Lower Parasitics
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Solution Overview
Problem
The challenge in the integrated circuit (IC) industry is to maintain gate control and reduce parasitic capacitance and contact resistance while scaling down IC technologies, as existing multigate devices face issues like increased parasitic capacitance, contact resistance, and short channel effects.
Innovation Solution
The method involves fabricating multigate devices with p-type and n-type GAA transistors, utilizing a specific semiconductor layer stack configuration, epitaxial source/drain features with bar-like or lollipop-like profiles, and airgaps to reduce parasitic capacitance and contact resistance, along with a detailed fabrication process that includes forming semiconductor fins, gate structures, and epitaxial growth to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication technologies are used for scaling, then manufacturing cost is reduced, but parasitic capacitance and contact resistance increase
Solution Approach 1:
The patent transitions from planar 2D device structures to three-dimensional FinFET structures with vertical channels. The fin configuration provides gate control from multiple directions (top and sidewalls), effectively reducing parasitic capacitance and contact resistance by utilizing the third dimension for improved electrical characteristics while maintaining scalability for conventional fabrication processes
Solution Approach 2:
The gate structure is positioned to surround the channel region in a nested configuration, with the gate wrapping around the fin structure. This nested arrangement maximizes gate control over the channel while minimizing parasitic effects, as the gate is conformally positioned to provide optimal electrical control without excessive capacitance
2Productivity
If IC dimensions are reduced to improve production efficiency, then manufacturing cost is lowered, but process complexity increases
Solution Approach 1:
The semiconductor structure is divided into multiple fins arranged in an array, with each fin providing an independent vertical channel. This segmentation allows the device to achieve high production efficiency through standardized repetitive structures while managing complexity through modular design that can be fabricated using conventional process steps
Solution Approach 2:
The FinFET structure serves multiple functions simultaneously: it provides enhanced gate control, reduces parasitic capacitance, maintains compatibility with conventional fabrication processes, and enables aggressive scaling. This multi-functionality resolves the contradiction by achieving productivity improvements without proportionally increasing process complexity
3Reliability
If gate structure extends around channel region to improve gate control, then short channel effects are reduced, but device structure complexity increases
Solution Approach 1:
The gate structure is configured to wrap around the fin channel in a curved or rounded manner rather than sharp angular connections. This curved gate configuration provides continuous gate control around the channel perimeter, effectively suppressing short channel effects while the smooth transitions reduce structural complexity compared to angular or discontinuous gate designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and contact resistance, enhancing the performance and scalability of multigate devices, thereby supporting the continued advancement of IC technologies.
Implementation Method 1
epitaxial source/drain features with bar-like or lollipop-like profiles
Data Source
AI summary
Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.