Multi-Gate Differential Power Amplifier for Parasitic Capacitance Stability

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Solution Overview

Problem

Conventional differential power amplifiers in RF environments face stability issues due to parasitic capacitances, which cannot be effectively addressed by existing multi-gate implementations.

Innovation Solution

A dual-gate differential power amplifier circuit is proposed, comprising a first differential power amplifier with cross-coupled neutralization capacitors and a second differential power amplifier with multi-gate transistors, both connected in parallel to improve stability and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional differential power amplifiers are used in RF environments, then the circuit can operate, but stability issues occur due to parasitic capacitances

Engineering Contradiction:
ImprovestabilityVSAvoidparasitic capacitances
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies neutralization capacitors that are cross-coupled between parallel branches to convert the harmful effect of parasitic capacitances into a beneficial effect. The neutralization capacitors create opposing capacitive effects that cancel out the parasitic capacitances, thereby improving stability while maintaining the original circuit operation.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent employs multi-gate transistors that integrate multiple gate structures into a single device. This composite transistor structure allows for independent control of different gate terminals, enabling better compensation of parasitic effects and improved overall stability in RF environments.

Inventive Principle:
Principle #40Composite materials

2Reliability

If multi-gate transistors are used to address parasitic capacitances, then stability improves, but device complexity increases

Engineering Contradiction:
ImprovestabilityVSAvoidmulti-gate transistor structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the control function by introducing multiple gates on the same transistor channel. Each gate can be independently controlled to perform specific functions such as signal modulation, bias control, or parasitic compensation, thereby managing complexity through functional segmentation rather than using entirely different transistor types.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multi-gate transistor structure serves multiple functions simultaneously: it acts as the main amplifying element, provides parasitic capacitance compensation through its additional gates, and enables independent bias control. This multi-functionality reduces the need for separate compensation circuits, thereby managing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If cross-coupled neutralization capacitors are added to compensate for parasitic effects, then stability improves, but device complexity increases

Engineering Contradiction:
ImprovestabilityVSAvoidneutralization capacitor configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the neutralization capacitor functions into the existing parallel branch architecture of the differential power amplifier. The capacitors are cross-coupled between the parallel branches, integrating the compensation function into the signal path rather than adding separate compensation circuits, thereby managing complexity through functional integration.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4535661A1Multi-gate differential power amplifier
Publication Date: 2025.04.09 GLOBALFOUNDRIES US INC
  • EP4535661A1 patent drawingFigure 1~3
  • EP4535661A1 patent drawingFigure 4
  • EP4535661A1 patent drawingFigure 5

AI summary

A differential power amplifier circuit (100), including: a first differential power amplifier (102) including first and second cross-coupled neutralization capacitors; and a second differential power amplifier (104), coupled in parallel with the first differential power amplifier (102), including a plurality of multi-gate transistors (106).