Multi-Gate Transistor Channel Doping for Lower Flicker Noise

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Solution Overview

Problem

The challenge in semiconductor manufacturing is the increased noise, such as flicker (1/f) noise, caused by interface and oxide traps in transistors, particularly in multi-gate devices like FinFETs, which degrades device performance and is exacerbated by the larger channel-to-gate dielectric interface surface area, leading to charge trapping and performance degradation.

Innovation Solution

The solution involves reducing the density of interface and oxide traps through a post-deposition anneal process and modulating the transistor channel current path to be farther away from the channel-to-gate dielectric interface, achieved by doping the transistor channel near the interface using techniques like ion implantation or ALD deposition, and employing a TiN capping layer to reduce oxygen absorption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multi-gate devices (FinFETs) are used to improve device performance and functionality, then the number of supported functions and device capability are improved, but noise (flicker noise) increases due to interface and oxide traps

Engineering Contradiction:
Improvedevice functionalityVSAvoidflicker noise
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

A nitrogen-containing dielectric layer is introduced as an intermediary between the gate dielectric and the channel region. This intermediate layer acts as a barrier that prevents oxygen from reaching the channel-dielectric interface, thereby reducing oxide traps and minimizing flicker noise while preserving the multi-gate device's enhanced functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs a nitrogen-containing dielectric material to create an inert environment that prevents oxygen absorption at the channel-dielectric interface. This inert atmosphere approach eliminates the formation of oxide traps that would otherwise generate flicker noise, allowing the device to maintain high performance with reduced noise

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Reliability

If the channel-to-gate dielectric interface surface area is increased in multi-gate devices, then device performance is improved, but charge trapping at the interface increases leading to performance degradation

Engineering Contradiction:
Improvedevice performanceVSAvoidcharge trapping
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The nitrogen-containing dielectric layer serves as a protective intermediary that prevents oxygen from reaching the channel-dielectric interface. By blocking oxygen transport, this intermediate layer eliminates the formation of oxide traps that would capture charge carriers, thereby reducing charge trapping effects while maintaining the benefits of increased interface surface area

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The nitrogen-containing dielectric layer is formed prior to subsequent processing steps, preemptively preventing oxygen absorption at the channel interface. This preliminary protective action ensures that oxide traps are prevented from forming in the first place, rather than attempting to remove them afterward

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively minimizes charge trapping and associated flicker noise, enhancing the performance of advanced transistor structures by reducing trap density and optimizing current paths.

Implementation Method 1

reducing the density of interface and oxide traps through a post-deposition anneal process

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

doping the transistor channel near the interface using techniques like ion implantation or ALD deposition

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20250015167A1Multi-gate device and related methods
Publication Date: 2025.01.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250015167A1 patent drawing
  • US20250015167A1 patent drawing
  • US20250015167A1 patent drawing

AI summary

A method of fabricating a semiconductor device includes providing a first fin extending from a substrate. In some embodiments, the method further includes forming a first gate stack over the first fin. In various examples, the method further includes forming a first doped layer along a surface of the first fin including beneath the first gate stack. In some cases, a first dopant species of the first doped layer is of a same polarity as a second dopant species of a source/drain feature of the semiconductor device.