Multi-Gate Channel Layer Tuning Across Logic, SRAM, and Analog
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Solution Overview
Problem
Existing semiconductor manufacturing processes struggle to provide multi-gate devices that meet diverse device performance requirements across different types, such as core (logic) devices, static random-access memory (SRAM) devices, and analog devices, while maintaining gate control and mitigating short-channel effects.
Innovation Solution
A method for fabricating multi-gate devices, like GAA transistors, with varying numbers of semiconductor channel layers selected based on the device type, using a single contiguous process flow, including steps like forming fins, shallow trench isolation, and forming gate structures to optimize performance for each device type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single multi-gate device structure is used for all device types, then manufacturing process simplicity is maintained, but diverse device performance requirements cannot be met
Solution Approach 1:
The patent applies local quality by allowing different numbers of semiconductor channel layers in different device regions. Specifically, first device type regions (e.g., core logic) have a first number of channel layers optimized for their performance requirements, while second device type regions (e.g., SRAM) have a second number of channel layers optimized for their different requirements. This enables each region to have locally optimized performance without requiring completely different device structures throughout the entire chip.
Solution Approach 2:
The patent segments the semiconductor chip into multiple device type regions, where each region can have independently optimized multi-gate devices. The chip is divided into first device type regions and second device type regions, with each region containing devices configured with appropriate numbers of channel layers for their specific function. This segmentation allows diverse performance optimization across different functional blocks while maintaining a unified manufacturing process.
2Speed
If the number of semiconductor channel layers is increased to meet performance requirements, then device speed and current are improved, but total device capacitance increases
Solution Approach 1:
The patent applies parameter changes by varying the number of semiconductor channel layers as a key design parameter to optimize different performance metrics. By adjusting this parameter differently in different device type regions, the patent achieves optimal device speed in regions where high performance is critical while minimizing total capacitance in regions where low power is more important. This parameter optimization is performed within the constraints of a single contiguous manufacturing process.
3Reliability
If multi-gate devices are used to improve gate control and reduce short-channel effects, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies universality by developing a single contiguous manufacturing process that can produce multi-gate devices with different numbers of channel layers for multiple device types. This universal process flow handles various device configurations (different channel layer counts for different device types) without requiring separate specialized manufacturing lines. The process achieves multi-functionality by accommodating diverse device requirements while maintaining process simplicity and consistency throughout fabrication.
Data Source
AI summary
A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.