Multi-Gate Channel Stack Partitioning for Leakage and Drive Current
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Solution Overview
Problem
Existing techniques have not satisfactorily addressed the challenge of providing multi-gate devices that meet diverse device performance requirements, such as low power consumption and high performance applications, particularly in GAA transistors, due to the complexity and high cost of fabrication processes.
Innovation Solution
The formation of GAA transistors with varying numbers of channel layers and dielectric features to meet specific application requirements, where low power consumption devices have fewer channel layers and high performance devices have more, achieved through selective etching and deposition processes to form distinct semiconductor structures in different device regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are introduced to improve gate control and reduce off-state current, then device performance is improved, but fabrication complexity and cost increase
Solution Approach 1:
The fabrication process is segmented into distinct regions (first device region and second device region) with different numbers of channel layers, allowing customized device performance while using a unified fabrication flow. This segmentation enables different device types to be manufactured simultaneously without requiring entirely separate fabrication processes.
Solution Approach 2:
Different regions of the substrate are given different local qualities by forming different numbers of channel layers in different device regions. The first device region receives a first number of channel layers while the second device region receives a second number of channel layers, allowing each region to be optimized for its specific application requirements.
2Adaptability or versatility
If diverse device performance requirements are met with different device types, then application versatility is improved, but manufacturing complexity increases
Solution Approach 1:
The fabrication process is designed to be universal and multi-functional, capable of producing different device types (low power consumption devices and high performance devices) within the same process flow. By forming different numbers of channel layers in different regions, a single fabrication process achieves multiple device performance outcomes.
Solution Approach 2:
Different device regions are assigned different local qualities through selective formation of channel layers. Low power consumption devices in the first device region receive a first number of channel layers optimized for low leakage, while high performance devices in the second device region receive a second number of channel layers optimized for high drive current.
3Power
If more channel layers are formed to enhance drive current, then device performance is improved, but leakage current increases
Solution Approach 1:
Different regions are given different local qualities by forming different numbers of channel layers. The first device region uses a first number of channel layers optimized for low leakage current, while the second device region uses a second number of channel layers optimized for high drive current, allowing each device type to have its performance characteristics locally optimized.
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a dielectric feature disposed directly on the substrate and in direct contact with a portion of the vertical stack of channel members, and a source/drain feature disposed directly on the dielectric feature and electrically coupled to a remaining portion of the vertical stack of channel members.