Multigate Cladding Structure for Footing-Free GAA Gate Fabrication

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Solution Overview

Problem

Existing gate-all-around (GAA) devices face challenges in fabricating a gate structure that leads to footing issues and diffusion into channels, degrading device performance and increasing processing complexity.

Innovation Solution

A method for fabricating multigate devices with an engineered cladding layer that includes forming a diffusion blocking layer before the cladding layer, using rapid thermal nitridation to convert a liner into silicon nitride, and selectively growing the cladding layer on semiconductor surfaces to prevent diffusion and eliminate footing issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a cladding layer is formed around an active region in conventional GAA devices, then the gate structure can be fabricated, but footing issues occur that cause residual defects during gate replacement

Engineering Contradiction:
Improvegate structure fabricationVSAvoidcladding layer footing
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

A liner layer is formed on the active region before the cladding layer is deposited. This preliminary liner layer prevents direct contact between the cladding layer and the active region, eliminating footing issues and residual defects during gate replacement while enabling successful gate structure fabrication

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If a cladding layer is formed around an active region, then the gate structure can be fabricated, but diffusion into channels occurs that reduces carrier mobility and degrades device performance

Engineering Contradiction:
Improvegate structure fabricationVSAvoiddevice performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A liner layer is introduced as an intermediary between the active region and the cladding layer. This liner layer acts as a diffusion barrier that prevents harmful diffusion into the channel while allowing the cladding layer to be formed for gate structure fabrication, thereby maintaining device performance

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If IC dimensions are reduced to improve production efficiency and lower costs, then manufacturing productivity increases, but manufacturing process complexity increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The cladding structure is segmented into multiple functional layers: a liner layer for protection and diffusion prevention, and a cladding layer for gate formation. This segmentation allows each layer to perform its specific function optimally, enabling continued scaling without proportionally increasing process complexity

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The engineered cladding layer enhances device performance by reducing diffusion and footing defects, improving gate control and processing efficiency in GAA devices.

Implementation Method 1

using rapid thermal nitridation to convert a liner into silicon nitride

Methodology Applied
Scientific EffectRapid thermal nitridation: Nitriding

Implementation Method 2

using rapid thermal nitridation to convert a liner into silicon nitride

Methodology Applied
Scientific EffectThermal diffusion: Diffusion

Implementation Method 3

selectively growing the cladding layer on semiconductor surfaces

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20250266290A1Multigate Device Structure with Engineered Cladding and Method Making the Same
Publication Date: 2025.08.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250266290A1 patent drawing
  • US20250266290A1 patent drawing
  • US20250266290A1 patent drawing

AI summary

The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.