Multigate Device Contact Resistivity Reduction via Doped Crystalline Layer
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Solution Overview
Problem
Parasitic resistance-capacitance (RC) delay has become a significant challenge in multigate devices as geometry sizes are reduced to achieve faster operating speeds, leading to increased source/drain contact resistance, which is not effectively addressed by current methods compatible with non-planar transistors.
Innovation Solution
A doped crystalline semiconductor layer, such as a gallium-doped germanium layer, is inserted between the source/drain feature and contact, formed by depositing a doped amorphous semiconductor layer and crystallizing it through annealing, without ion implantation or epitaxial growth, to reduce contact resistivity at the metal-semiconductor interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If geometry sizes are reduced to achieve faster operating speeds, then operating speed is improved, but source/drain contact resistance increases
Solution Approach 1:
The patent applies local quality by creating a doped crystalline semiconductor layer with high dopant concentration specifically at the contact interface region, while maintaining different doping levels in other regions. This localized high-doping approach reduces contact resistivity at the metal-semiconductor interface without requiring uniform high doping throughout the entire device, thus resolving the contradiction between reduced geometry and increased contact resistance.
Solution Approach 2:
The patent changes the doping concentration parameter locally at the contact interface by forming a doped crystalline semiconductor layer with dopant concentration exceeding solid solubility limits. This parameter change (from standard doping to ultra-high doping) directly reduces contact resistivity, allowing the device to maintain low contact resistance even as overall geometry is reduced for faster operation.
2Reliability
If current contact resistivity reduction methods are used, then contact resistivity is reduced, but compatibility with non-planar transistor fabrication is lost
Solution Approach 1:
The patent replaces mechanical/ion implantation methods with a deposition-based approach. Instead of using ion implantation (which is incompatible with non-planar surfaces), the invention uses physical vapor deposition or chemical vapor deposition to form the doped crystalline semiconductor layer conformally on the three-dimensional contact structure, maintaining fabrication compatibility while achieving contact resistivity reduction.
Solution Approach 2:
The patent introduces a doped crystalline semiconductor layer as an intermediary between the metal contact and the underlying semiconductor. This intermediate layer serves as a transition region that facilitates charge carrier transport and reduces contact resistivity, while its conformal deposition nature ensures compatibility with non-planar transistor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistivity to less than 1×10−9 Ω-cm2, improving performance while being compatible with conventional multigate device fabrication and avoiding damage from high thermal budgets.
Implementation Method 1
crystallizing it through annealing
Implementation Method 2
crystallizing it through annealing
Data Source
AI summary
An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10−9 Ω-cm2.