Multi-Gate Transistor Contacts With 3D Source/Drain Interface
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Solution Overview
Problem
Conventional contact formation schemes in highly scaled multi-gate FETs result in elevated transistor contact resistance, limiting device performance beyond 50%.
Innovation Solution
The method involves forming deep contact holes that expose multiple surfaces of the source/drain regions, followed by the deposition of a conformal first contact layer with low energy barrier materials and a subsequent second contact layer to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation schemes are used in highly scaled multi-gate FETs, then manufacturing process simplicity is maintained, but contact resistance increases significantly limiting device performance
Solution Approach 1:
The contact hole etching process transitions from conventional planar etching to three-dimensional vertical etching that exposes multiple surfaces (top surface and sidewalls) of the source/drain regions. This dimensional change in the contact hole geometry enables significantly reduced contact resistance by creating additional contact interfaces between the contact plug and the semiconductor region, while the process itself remains integrated into the existing fabrication flow.
Solution Approach 2:
The contact hole is designed with non-uniform geometry where the depth and sidewall exposure are specifically optimized to maximize the contact area with the source/drain regions. The etch process creates localized exposure of multiple surfaces at the contact region without affecting other areas of the device, allowing reduced contact resistance precisely where needed while maintaining overall process compatibility.
2Reliability
If deep contact holes exposing multiple surfaces are formed, then contact resistance is reduced significantly, but manufacturing precision requirements increase
Solution Approach 1:
A conformal first contact layer is deposited as an intermediary between the deep contact hole structure and the subsequent second contact layer. This first contact layer uniformly coats all exposed surfaces (top surface and sidewalls) of the source/drain regions, ensuring consistent electrical contact across the complex three-dimensional geometry. The conformal deposition process naturally adapts to the varying surface orientations, reducing the precision requirements for the etching step while achieving uniform low-resistance contact.
Solution Approach 2:
The contact hole etching process parameters are optimized to achieve the desired depth and sidewall exposure geometry. By controlling etch depth, etch rate, and selectivity, the process creates the optimal three-dimensional contact structure that maximizes surface area for electrical contact. The conformal layer deposition then adapts to these geometric parameters, ensuring uniform coverage regardless of the specific etch dimensions achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces contact resistance, achieving contact resistivity in the range of 1×e−10 to 1×e−8 ohm·cm2, thereby enhancing the intrinsic performance of multi-gate transistors.
Implementation Method 1
forming a conformal first contact layer over the source/drain regions
Implementation Method 2
deposition of a conformal first contact layer
Data Source
AI summary
A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.