Multi-Gate Semiconductor Contacts for Lower Resistance GAA FETs
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Solution Overview
Problem
Existing GAA FET devices face challenges in achieving optimal control over the channel region due to the uncontrolled bottom side, leading to increased contact resistance and inferior current spreading, which affects device performance in high-density integrated circuits.
Innovation Solution
The method involves forming multi-gate semiconductor structures with nanowires and gate structures around them, using a combination of photolithography and self-aligned processes to create recesses and metal silicide layers, which reduces contact resistance by optimizing the metal contact area and current spreading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate electrode is positioned adjacent to three side surfaces of a channel region (FinFET configuration), then the transistor achieves three-gate control, but the bottom part of the channel region is far away from the gate electrode and not under close gate control
Solution Approach 1:
The patent transitions from a planar FinFET structure to a three-dimensional gate-all-around (GAA) nanowire structure where the gate electrode completely surrounds the channel region in multiple dimensions. This dimensional change allows the gate to control all surfaces of the channel including the bottom, achieving uniform electrostatic control from all directions rather than just three sides as in FinFET.
Solution Approach 2:
The gate electrode is positioned inside and around the channel region in a nested configuration, with the gate completely surrounding the channel in a GAA structure. This nested arrangement allows the gate to be in close proximity to all surfaces of the channel, including the bottom, enabling complete electrostatic control of the channel region.
2Ease of manufacture
If the bottom part of the channel region is positioned far away from the gate electrode, then the structure is simpler to fabricate, but contact resistance increases and current spreading is inferior
Solution Approach 1:
The patent employs a three-dimensional GAA nanowire structure where the gate completely surrounds the channel, creating multiple contact pathways for current in vertical and lateral dimensions. This multi-dimensional current spreading reduces contact resistance by providing numerous parallel conduction paths from the source/drain to the gate, overcoming the limitations of planar structures.
Solution Approach 2:
The gate electrode is formed as a thin film that completely wraps around the nanowire channel in a conformal configuration. This thin film gate structure maintains close proximity to all surfaces of the channel while allowing efficient current spreading and reducing contact resistance through the large surface area contact between gate and channel.
3Ease of manufacture
If existing GAA FET devices are used, then the fabrication process is established, but the uncontrolled bottom side of the channel region leads to inferior device performance
Solution Approach 1:
The patent implements a true three-dimensional gate-all-around structure where the gate electrode completely surrounds the nanowire channel in all directions including bottom control. This dimensional advancement provides complete electrostatic control of the channel region, eliminating the uncontrolled bottom side present in planar structures and significantly improving device performance through uniform depletion and reduced short-channel effects.
Solution Approach 2:
The gate electrode is nested inside and around the channel region in a concentric configuration, with the gate completely surrounding the nanowire. This nested GAA structure ensures that the gate is in close proximity to all surfaces of the channel, providing complete control over the channel region and enabling superior electrostatic control and device performance.
Data Source
AI summary
Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.