Multigate Epitaxial Source/Drain Structures on Dielectric Substrates
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Solution Overview
Problem
Existing multigate devices face challenges in optimizing reliability as they continue to scale down, with conventional fabrication methods not adequately addressing issues such as parasitic transistors and leakage current due to epitaxial source/drain structures contacting semiconductor substrates.
Innovation Solution
The introduction of epitaxial source/drain structures that physically contact a dielectric substrate instead of a semiconductor substrate, featuring varying dopant concentrations and compositions to enhance performance by suppressing parasitic transistors and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epitaxial source/drain structures contact semiconductor substrates in conventional multigate devices, then manufacturing process is simplified, but parasitic transistors form and leakage current increases
Solution Approach 1:
The patent introduces a dielectric substrate as an intermediary between the epitaxial source/drain structures and the underlying substrate. This dielectric layer prevents direct contact that would form parasitic transistors, while still allowing the epitaxial structures to be formed using standard processes. The dielectric substrate acts as a mediator that eliminates the harmful parasitic effects without complicating the overall fabrication flow.
Solution Approach 2:
The patent extracts the problematic semiconductor substrate interface and replaces it with a dielectric substrate. By removing the semiconductor-substrate contact, the source of parasitic transistor formation is eliminated. The epitaxial source/drain structures are now grown on a dielectric surface rather than a semiconductor surface, which prevents the formation of unwanted parasitic devices while maintaining the desired electrical functionality.
2Productivity
If multigate devices continue to scale down, then device density and integration increase, but gate control and reliability become harder to maintain
Solution Approach 1:
The patent changes the fundamental parameter of the substrate material from semiconductor to dielectric. This parameter change fundamentally alters the electrical characteristics at the source/drain interface, preventing parasitic transistor formation that would otherwise become increasingly problematic as devices scale. The dielectric substrate provides a non-conductive foundation that maintains gate control even as device dimensions shrink and density increases.
Solution Approach 2:
The patent applies preliminary anti-action by pre-establishing a dielectric substrate before forming the epitaxial source/drain structures. This preliminary measure prevents the formation of parasitic transistors before they can occur, countering the scaling-induced increase in parasitic effects. By acting in advance with the dielectric substrate, the patent prevents reliability degradation as devices continue to scale down for higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves device performance by eliminating parasitic transistors and reducing leakage current, thereby enhancing the reliability and efficiency of multigate devices like fin-like FETs and gate-all-around FETs.
Implementation Method 1
epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs
Data Source
AI summary
Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.


