Multigate Epitaxial Source/Drains for Contact Alignment

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Solution Overview

Problem

As IC feature sizes shrink, multigate devices face challenges with epitaxial source/drain configurations that lead to unintentional merging, electrical shorting, and performance degradation due to reduced contact landing windows and alignment issues, particularly in FinFETs and GAA transistors.

Innovation Solution

Optimized lateral dimensions and spacings for epitaxial source/drains are implemented to maximize contact landing windows, minimize merging, and reduce residue, accounting for different type FinFETs and additional isolation, with configurations tailored for advanced technology nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If epitaxial source/drain configurations are used for scaled multigate devices, then device density and integration are improved, but unintentional merging and electrical shorting occur due to reduced contact landing windows

Engineering Contradiction:
Improvedevice densityVSAvoidelectrical shorting
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the treatment of epitaxial source/drain regions based on their spatial location and functional requirements. Different epitaxial growth conditions, doping concentrations, and lateral dimensions are applied to different regions (e.g., first epitaxial source/drain versus second epitaxial source/drain) to optimize contact landing windows in specific locations while preventing merging in others. This localized optimization allows high device density while maintaining electrical isolation where needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the epitaxial source/drain structure into distinct regions (first epitaxial source/drain, second epitaxial source/drain, and isolation regions) with different properties. By dividing the continuous epitaxial growth into separate, controlled segments, the patent prevents unintentional merging between adjacent devices while maintaining the benefits of scaled-down dimensions for high density. The segmentation is achieved through controlled epitaxial growth patterns and isolation barrier layers.

Inventive Principle:
Principle #1Segmentation

2Length of moving object

If epitaxial source/drain lateral dimensions are reduced for smaller IC feature sizes, then device scaling is achieved, but contact alignment precision deteriorates

Engineering Contradiction:
Improvefeature sizeVSAvoidcontact alignment
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming mandrels and sacrificial structures before the final epitaxial source/drain regions. These preliminary structures serve as alignment references and define the precise locations for subsequent epitaxial growth. The mandrels are positioned and aligned in advance, providing a framework that guides the formation of accurately positioned epitaxial regions even at reduced feature sizes, thereby maintaining contact alignment precision during scaling.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses intermediary structures (such as mandrels, sacrificial layers, and isolation barriers) as mediators between the lithography patterning process and the final epitaxial source/drain formation. These intermediary elements translate the lithography patterns into precisely defined epitaxial growth regions, buffering the sensitivity to alignment errors. The intermediaries provide mechanical and chemical guidance that ensures accurate epitaxial placement even when feature sizes are reduced below the lithography resolution limit.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If epitaxial growth is optimized for lateral extension, then contact landing windows are maximized, but merging with adjacent devices increases

Engineering Contradiction:
Improvecontact landing windowVSAvoidunintentional merging
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by optimizing epitaxial lateral extension differently in different spatial locations. In regions requiring large contact landing windows (e.g., under gate structures), the epitaxial growth is encouraged to extend laterally. In regions adjacent to other devices, the epitaxial growth is constrained or terminated to prevent merging. This spatially varying optimization is achieved through controlled epitaxial growth conditions, selective doping, and isolation barrier layers positioned at specific locations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses isolation barrier layers and sacrificial structures as intermediaries to control epitaxial lateral extension. These intermediary layers act as growth barriers or selective etch stop layers that define where epitaxial material can and cannot extend. By strategically placing these intermediaries between adjacent device regions, the patent enables large contact landing windows in isolated regions while preventing epitaxial merging in proximity to other devices.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances device density and performance by preventing unintentional merging and improving contact alignment, while maintaining reliable operation and reducing short channel effects.

Implementation Method 1

epitaxial source/drain configurations, epitaxial source/drains 30 disposed over the recessed portions of fin 15

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20250338544A1Epitaxial Source/Drain Configurations for Multigate Devices
Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250338544A1 patent drawing
  • US20250338544A1 patent drawing
  • US20250338544A1 patent drawing

AI summary

A semiconductor structure includes a first multigate device, a second multigate device, and an isolation structure. The first multigate device has a first channel layer extending between first epitaxial source/drains along a first direction. The second multigate device has a second channel layer extending between second epitaxial source/drains along the first direction. The first epitaxial source/drains and second epitaxial source/drains have a first width and a second width, respectively, along a second direction that is different than the first direction. The isolation structure includes a dielectric fin over a substrate isolation feature. The dielectric fin is between the first epitaxial source/drains and the second epitaxial source/drains. The dielectric fin has a third width along the second direction. A distance between the first epitaxial source/drains and the second epitaxial source/drains along the second direction is greater than the third width, less than the second width, and less than the first width.