Multi-Gate Ferroelectric Memory for Single-Element Array Selection
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Solution Overview
Problem
Existing ferroelectric memory arrays require two elements to select the storage state, leading to increased surface area and cost, and existing Flash technology with a three-layer structure is slow in changing the storage state.
Innovation Solution
A multi-gate ferroelectric memory device with a fin-shaped channel layer, front and back ferroelectric layers, and independent front and back gates connected to word and bit lines, allowing for selective storage state changes using one element and reducing the size and cost of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two elements (transistor and memory element) are used to implement a memory cell for selecting storage state, then the storage state can be selected, but the surface area of the memory array increases
Solution Approach 1:
The patent combines the selection function and storage function into a single memory element by integrating the transistor gate with the ferroelectric memory cell. The front gate and back gate of the FinFET structure serve dual purposes as both selection switches and storage control mechanisms, eliminating the need for separate selection transistors and reducing the number of elements per memory cell from two to one.
Solution Approach 2:
The memory element is designed to perform multiple functions: the front gate controls word line selection while the back gate controls bit line selection, and both gates simultaneously manage the storage state through the ferroelectric layer. This multi-functional design allows a single element to replace what traditionally required two separate elements.
2Device complexity
If Flash technology with three-layer structure is used to change storage state through quantum tunneling or hot carriers, then only one element is needed, but the speed of changing storage state is slow
Solution Approach 1:
The patent changes the operating mechanism from quantum tunneling or hot carrier injection (Flash technology) to direct ferroelectric polarization switching. By applying voltage through the front and back gates, the ferroelectric layer rapidly switches between polarization states, achieving fast storage state changes while maintaining the single-element structure.
Solution Approach 2:
The memory element uses a composite structure combining FinFET transistor architecture with ferroelectric material layers. This composite design integrates the electrical control capability of the transistor with the fast switching properties of ferroelectric materials, achieving both single-element simplicity and high-speed operation.
3Device complexity
If conventional memory structure is used, then the structure is simple, but more elements are required leading to increased cost
Solution Approach 1:
The patent merges multiple functional elements into a single integrated structure where the FinFET transistor and ferroelectric memory cell share common components. The front gate and back gate structures serve both as transistor control electrodes and as interfaces for ferroelectric polarization control, reducing the total element count and manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables faster storage state alterations and lower power consumption, with each memory operating independently under lower working voltage, reducing the overall size and cost of the memory array while increasing storage density.
Implementation Method 1
with the ferroelectric material, the storage state of the memory may be altered faster and the memory may operate under a lower working voltage
Data Source
AI summary
A multi-gate ferroelectric memory comprises a fin-shaped channel layer, a front ferroelectric layer disposed on one side of the fin-shaped channel layer, a back ferroelectric layer disposed on another side of the fin-shaped channel layer, a front gate attached to the front ferroelectric layer and away from the fin-shaped channel layer, wherein the front gate is configured to connect a word line, and a back gate attached to the back ferroelectric layer and away from the fin-shaped channel layer, wherein the back gate is configured to connect a bit line. The present disclosure further discloses a memory array device, comprises a plurality of the multi-gate ferroelectric memories arranged as an array, a plurality of word lines and a plurality of bit lines.