Multi-Gate FET Gate Electrode Metal Contamination Prevention
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Solution Overview
Problem
Conventional multi-gate field effect transistors face issues with metal contamination and uneven natural oxide films during the manufacturing process, leading to degraded device performance and variations in threshold values, which are critical for high-frequency operations.
Innovation Solution
A method involving the formation of semiconductor layers, protection films, and insulating layers to create a multi-gate field effect transistor structure where polysilicon films are used to fill holes and form gate electrodes, with siliciding and metal connecting portions, while preventing metal contamination through controlled etching and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate or silicide gate is used in a multi-gate field effect transistor, then the gate electrode can control the channel potential effectively, but metal contamination occurs during the flattening process which degrades device performance
Solution Approach 1:
The patent introduces a polysilicon film as an intermediary layer between the metal gate/silicide gate and the channel region. This polysilicon layer serves as a protective barrier that prevents metal contamination during the flattening process while still allowing effective gate control. The metal gate is formed first, then polysilicon is deposited over it, and finally the polysilicon is flattened by CMP to provide a planar surface for subsequent processing without exposing the metal to contamination.
Solution Approach 2:
The patent performs the flattening operation on the polysilicon layer before forming the source and drain regions. This preliminary flattening action creates a planar surface that enables accurate lithographic patterning of the source and drain regions without metal contamination risk. The sequence is: form metal gate, deposit polysilicon, flatten polysilicon, then proceed with source/drain formation.
2Manufacturing precision
If a natural oxide film is present on the gate electrode, then the gate structure is protected, but the oxide film cannot be removed by conventional methods leading to threshold value variations
Solution Approach 1:
The polysilicon film acts as an intermediary that eliminates the need to directly handle the natural oxide film on the metal gate. Since the polysilicon is deposited over the metal gate and then flattened, the oxide film remains trapped underneath the polysilicon layer where it does not interfere with device operation. The threshold value is controlled by the polysilicon-gate structure rather than the metal-oxide interface.
3Productivity
If the gate length is reduced to achieve smaller device sizes, then the integration density increases, but the potential barrier reduction and leakage current increase
Solution Approach 1:
The patent uses a composite gate structure consisting of metal gate, silicide gate, or polysilicon gate combined with gate insulating film and protection film. This composite structure provides enhanced gate control over the channel region. The multi-layer gate structure with different materials having different work functions and electrical properties enables better potential control and higher barrier against leakage current compared to simple single-material gates.
Solution Approach 2:
The patent transitions from a planar single-gate structure to a three-dimensional multi-gate structure where gate electrodes are formed on multiple sides of the channel region (top, bottom, and sidewalls). This dimensional change provides control of the channel potential from multiple directions, significantly enhancing the gate's ability to control carrier flow and block leakage current even in short-channel devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents metal contamination and reduces gate resistance, enabling the formation of small-sized gates without flattening, thereby improving device performance and reducing variations in threshold values, enhancing high-frequency operations.
Implementation Method 1
forming a gate insulating film on both side faces of the semiconductor layer inside the holes
Implementation Method 2
depositing a first polysilicon film on an entire surface to fill the holes
Implementation Method 3
implanting an impurity into the selectively exposed semiconductor layers to form source and drain regions
Data Source
AI summary
A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.