Multi-Gate FET Leakage Reduction via Dynamic Channel Length
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Solution Overview
Problem
Field effect transistors in memory arrays face challenges with high leakage current in the 'off' state due to short channel lengths, which affects circuit density and power consumption.
Innovation Solution
The use of transition metal dichalcogenide materials for channel regions and mid-gates, with strategically positioned outer and inner gates electrically isolated by dielectric materials, allows for dynamic adjustment of effective channel length to minimize leakage current and optimize performance in both 'on' and 'off' states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel region length is made short to maximize operating speed and circuit density, then the transistor operating speed and circuit density are improved, but the leakage current in the off state increases
Solution Approach 1:
The patent implements a multi-gate configuration (outer gate and inner gate) that enables dynamic control of the effective channel length. By independently controlling the outer gate and inner gate voltages, the effective channel length can be adjusted to optimize performance: shorter effective channel length for high-speed operation and longer effective channel length for reduced leakage current, thus resolving the contradiction between speed and leakage.
2Productivity
If the channel region length is made short to maximize circuit density, then the circuit density is improved, but the leakage current in the off state increases
Solution Approach 1:
The multi-gate structure allows dynamic adjustment of effective channel length to simultaneously achieve high circuit density and low leakage current. The inner gate can extend the effective channel length vertically when leakage reduction is needed, while maintaining the short horizontal channel length for high density, thus resolving the contradiction between density and leakage.
3Speed
If the channel region length is made short to maximize operating speed, then the operating speed is improved, but the power consumption increases due to higher leakage current
Solution Approach 1:
The patent employs a multi-gate configuration that enables dynamic control of effective channel length. During active operation, the gates are biased to provide short effective channel length for high speed. During idle or standby states, the gates can be adjusted to increase effective channel length, reducing leakage current and thus power consumption, while maintaining the physical short channel structure for speed capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leakage current in the 'off' state, enhances circuit density, and lowers power consumption by dynamically varying the effective channel length, improving the overall efficiency of memory arrays.
Implementation Method 1
Gate dielectric is laterally between a) the channel region, and b) the mid-gate and the outer and inner gates
Implementation Method 2
These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between
Implementation Method 3
Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region
Data Source
AI summary
A field effect transistor construction comprises two source/drain regions and a channel region there-between. The channel region comprises a transition metal dichalcogenide material having a thickness of 1 monolayer to 7 monolayers and having a physical length between the source/drain regions. A mid-gate is operatively proximate a mid-portion of the channel region relative to the physical length. A pair of gates is operatively proximate different respective portions of the channel region from the portion of the channel region that the mid-gate is proximate. The pair of gates are spaced and electrically isolated from the mid-gate on opposite sides of the mid-gate. Gate dielectric is between a) the channel region, and b) the mid-gate and the pair of gates. Additional embodiments are disclosed.