Multi-gate FET Logic Gates for High-Density Integration
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Solution Overview
Problem
Conventional digital logic circuits face challenges in reducing the area occupied by each logic gate, as increasing the size of stacked devices to reduce ON resistance limits the number of inputs that can be realized in NAND and NOR gates.
Innovation Solution
The use of multi-gate FETs in logic gates, where a first portion is configured to interconnect the output with either the voltage supply or ground upon input activation, and a second portion, comprising a multi-gate FET of a different type, conducts logically only when both gates are activated, allowing for higher-density logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of stacked devices is increased to reduce ON resistance, then the ON resistance decreases, but the area occupied by each logic gate increases
Solution Approach 1:
The patent merges multiple gate functions into a single multi-gate FET structure. Instead of using separate stacked devices for each input, the invention integrates multiple gates (first gate and second gate) onto a single FET channel, allowing logical AND functionality while reducing the overall device area and maintaining low ON resistance.
Solution Approach 2:
The patent transitions from a planar single-gate structure to a three-dimensional multi-gate structure. The multi-gate FET employs gates positioned on multiple surfaces (e.g., top and bottom gates, or gates on multiple sides of a FinFET channel), effectively utilizing vertical and lateral dimensions to enhance control over the channel while compacting the footprint area.
2Reliability
If the size of stacked devices is increased to reduce ON resistance, then the ON resistance decreases, but the number of inputs that can be realized is limited
Solution Approach 1:
The patent combines multiple input control functions into a single multi-gate FET device. The first gate and second gate of the multi-gate FET work together to provide logical AND functionality for multiple inputs, eliminating the need for additional stacked devices and thereby supporting more inputs without increasing device stack height or limiting input scalability.
Solution Approach 2:
The multi-gate FET structure serves multiple functions simultaneously: it provides logical AND operation for multiple inputs, maintains low ON resistance, and enables high-density integration. This universal structure can be applied to various logic gate configurations (NAND, NOR, etc.) and input counts, making the device highly versatile and scalable.
3Reliability
If conventional stacked devices are used, then the logical functionality is maintained, but the area occupied by each logic gate increases
Solution Approach 1:
The patent merges the functionality of multiple conventional stacked devices into a single multi-gate FET. The first portion (conventional FET) and second portion (multi-gate FET) work together to achieve the same logical functionality as traditional stacked configurations, but with significantly reduced area due to the compact multi-gate structure.
Solution Approach 2:
The invention moves from two-dimensional planar device stacking to three-dimensional multi-gate configurations. By positioning gates on multiple surfaces and utilizing vertical channel structures, the patent achieves enhanced logical control and higher density within a smaller footprint area, effectively breaking the area-scaling limitation of conventional approaches.
Data Source
AI summary
Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.