Multi-Gate FET Source Convexity for Lower Resistance and Capacitance
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Solution Overview
Problem
Field Effect Transistors (FETs) face a trade-off between reducing source resistance and minimizing parasitic capacitance, making it difficult to improve FET characteristics, as shortening the distance between the source region and the gate increases parasitic capacitance, thereby degrading performance.
Innovation Solution
A semiconductor device with a source region having a convexity that protrudes towards the drain region between adjacent gates, embedded from the upper surface to the channel layer, which reduces source resistance while maintaining a balanced parasitic capacitance, thereby enhancing FET characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between the source region and the gate is shortened to reduce source resistance, then source resistance decreases, but parasitic capacitance increases
Solution Approach 1:
The source region is designed with non-uniform doping concentration, featuring a high-doping concentration region near the gate and a low-doping concentration region extending toward the drain. This local quality variation allows the high-doping region to reduce source resistance where it matters most (near the gate), while the low-doping region maintains smaller parasitic capacitance by reducing excess carriers in the extended region.
Solution Approach 2:
The invention transitions from a one-dimensional uniform doping model to a two-dimensional spatially-varying doping profile. By introducing the dimension of doping concentration gradient across the source region length, the design simultaneously optimizes both source resistance (benefiting from high doping near gate) and parasitic capacitance (benefiting from low doping in extended regions).
Data Source
AI summary
A semiconductor device includes a semiconductor layer provided on a substrate and including a channel layer, a source region connected to the channel layer and having a sheet resistance smaller than a sheet resistance of the channel layer, a drain region connected to the channel layer and having a sheet resistance smaller than the sheet resistance of the channel layer, a plurality of gates provided between the source region and the drain region, arranged in a direction intersecting an arrangement direction of the source region and the drain region, and embedded from an upper surface of the semiconductor layer to at least the channel layer, wherein a part of the source region has a convexity that faces a region between two adjacent gates among the plurality of gates, and protrudes toward a part of the drain region through the region between the two adjacent gates.