Multi-gate FET Switching Device Harmonic Reduction
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Solution Overview
Problem
Conventional high-frequency switching devices face challenges in achieving increased power handling capability while minimizing harmonic output, particularly third harmonic amplitude, which is not adequately reduced by existing capacitor configurations, and occupy significant semiconductor die area due to the need for multiple FETs.
Innovation Solution
The implementation of a high-frequency switching device with multi-gate FETs and strategically placed capacitors between gate and drain, and gate and source, along with resistors, to attenuate voltage swings and reduce harmonic amplitude, combined with setting source and drain voltages to a common DC voltage to enhance control and reduce harmonic generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of FETs in each switching block is increased to achieve increased power handling capability, then the power handling capability is improved, but the semiconductor die area consumed by the switching device increases
Solution Approach 1:
Multiple FETs are combined in a parallel configuration within each switching block, merging their current handling capabilities while sharing common source and drain regions. This allows the device to achieve increased power handling capability without proportionally increasing the semiconductor die area, as the merged structure utilizes shared regions efficiently.
2Object-generated harmful factors
If capacitors are coupled between gate and drain, and gate and source of FETs to reduce harmonic output, then the harmonic amplitude is reduced, but the device complexity increases
Solution Approach 1:
Capacitors are strategically placed only at specific locations within the switching device - between the gate and drain, and between the gate and source of the FETs in each switching block. This localized application of harmonic reduction components achieves effective harmonic suppression while minimizing the overall device complexity compared to a comprehensive approach applied throughout the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces third harmonic amplitude, allows operation at lower control voltages, increases power handling capability, and reduces semiconductor die area occupancy compared to conventional designs.
Implementation Method 1
A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET
Data Source
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AI summary
According to one exemplary embodiment, a low harmonic switching device (200) includes a first switching block (202) including a first multi-gate FET (206), where the first switching block is coupled to a first input (262) and a shared output (270) of the low harmonic switching device. A first capacitor (214) is coupled between a first gate and a source of the first multi-gate FET and a second capacitor (216) is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor (220) can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET (208), where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.