Multigate FET Voids Reduce Parasitic Capacitance

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Solution Overview

Problem

As semiconductor devices miniaturize, parasitic capacitances between fin-shaped structures in multigate field effect transistors increase, degrading electrical performance.

Innovation Solution

Forming voids in a dielectric layer between fin-shaped structures to reduce parasitic capacitances, which involves creating a dielectric layer with specific voids between the fin-shaped structures during the manufacturing process of multigate field effect transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the dielectric layer is fully filled between fin-shaped structures, then the manufacturing process is simpler and more complete, but the parasitic capacitances between fin-shaped structures increase, degrading electrical performance

Engineering Contradiction:

Improveelectrical performanceVSAvoiddielectric layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies porous materials by forming voids within the dielectric layer between fin-shaped structures. This creates a porous dielectric structure that reduces parasitic capacitance while maintaining the dielectric layer's insulating function. The voids are strategically positioned to minimize capacitance without compromising structural integrity or requiring complex manufacturing processes.

Inventive Principle:

Principle #31Porous materials

2Reliability

If voids are formed in the dielectric layer between fin-shaped structures, then parasitic capacitances are reduced and electrical performance is enhanced, but the manufacturing process becomes more complex

Engineering Contradiction:

Improveelectrical performanceVSAvoidprocessing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies partial action by forming voids only in specific regions of the dielectric layer where parasitic capacitance is most problematic, rather than completely removing dielectric material throughout. This selective approach reduces capacitance effectively while minimizing the complexity and cost of the manufacturing process.

Inventive Principle:

Principle #16Partial or excessive action

3Power

If the channel region is made longer for the same gate length, then the current between source and drain is increased, but the device area increases

Engineering Contradiction:

Improvecurrent between source and drainVSAvoiddevice area

Core Design Contradiction:

PowerVSArea of stationary object

Solution Approach 1:

The patent applies dimensionality change by transitioning from a planar channel structure to a three-dimensional multi-gate structure with fin-shaped channels. This vertical stacking approach increases the effective channel length and gate control area without proportionally increasing the lateral device footprint, thereby increasing current capability while controlling device area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9159831B2Multigate field effect transistor and process thereof

Publication Date: 2015.10.13 MARLIN SEMICON LTD

AI summary

A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.