Multi-Gate Fin Structure With Asymmetric Trenches for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling density and improving current control capability while effectively suppressing short channel effects.
Innovation Solution
The semiconductor device incorporates a multi-gate transistor with fin and/or nanowire structures on a substrate, featuring deep trenches and fin-type patterns of varying depths and conductive types, along with a field insulating film and gate electrodes to enhance performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors with three-dimensional channels are used for scaling, then device density and current control capability are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The device is divided into multiple fins (first fin, second fin, third fin) with different depths, creating a multi-gate structure that provides three-dimensional channel control. This segmentation allows improved current control and SCE suppression while maintaining manufacturability through systematic formation processes
Solution Approach 2:
The invention transitions from two-dimensional planar channels to three-dimensional vertical fins with varying depths. The different fin depths create additional control dimensions for current modulation and short channel effect suppression, enabling better performance in scaled devices
2Reliability
If gate length is increased to improve current control, then current control capability improves, but device area increases
Solution Approach 1:
Instead of increasing gate length in the planar direction, the invention uses vertical fins with different depths to achieve current control. The multi-gate structure provides control from multiple directions (top and sidewalls), enabling effective current modulation without increasing the lateral device footprint
3Ease of manufacture
If uniform depth trenches are used for simplicity, then manufacturing simplicity is maintained, but current control and short channel effect suppression are reduced
Solution Approach 1:
Different regions of the device have fins with different depths (first fin with first depth, second fin with second depth, third fin with third depth). This local variation in fin depth allows optimized current control and SCE suppression in specific regions while maintaining overall device functionality
Solution Approach 2:
The invention employs asymmetric fin depths where the first fin, second fin, and third fin have different depths from each other. This asymmetry creates diverse current paths and control mechanisms, improving short channel effect suppression compared to uniform depth structures
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate, a first base fin protruding from the substrate and extending in a first direction, and a first fin type pattern protruding from the first base fin and extending in the first direction. The first base fin includes a first sidewall and a second sidewall, the first and second sidewalls extending in the first direction, the first sidewall opposite to the second sidewall, the first sidewall of the first base fin at least partially defines a first deep trench, the second sidewall of the first base fin at least partially defines a second deep trench, and a depth of the first deep trench is greater than a depth of the second deep trench.