Multi-Gate Fin Structure for Uniform EOT and Threshold Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down FinFETs due to the critical need for precise control of the thickness and uniformity of interfacial layers in high-k/metal gate stacks, which affects the equivalent oxide thickness (EOT) and threshold voltage of FinFETs.
Innovation Solution
A method for forming multi-gate transistors involves growing a strain relaxed buffer layer over a substrate, forming fin elements with semiconductor layers, and creating an interfacial layer and high-k dielectric layer structure around the channel regions, followed by a scavenging process to optimize the interfacial layer and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFETs are scaled down to nanometer technology nodes, then device density and performance are improved, but control of equivalent oxide thickness (EOT) and interfacial layer uniformity becomes increasingly difficult
Solution Approach 1:
The channel region is divided into multiple segments by removing portions of the second semiconductor layer, creating spaced-apart first and third semiconductor layers. This segmentation allows independent formation and control of multiple interfacial layers (first interfacial layer between first channel and gate, second interfacial layer between third channel and gate), enabling precise control of EOT and uniformity in each segment while maintaining high device density.
2Reliability
If the interfacial layer thickness is reduced to improve EOT, then device performance is enhanced, but the layer becomes more sensitive to non-uniformity affecting threshold voltage
Solution Approach 1:
Different interfacial layers are formed with different thicknesses and materials tailored to local requirements. The first interfacial layer and second interfacial layer can have different thicknesses and compositions, allowing optimization of EOT in high-performance regions while ensuring uniformity in regions sensitive to threshold voltage control.
3Ease of manufacture
If conventional planar device structures are used, then fabrication is simpler, but short channel effects and leakage increase at nanometer nodes
Solution Approach 1:
The device structure transitions from a conventional planar configuration to a multi-gate FinFET structure where the gate wraps around the channel in three dimensions. This dimensional change provides superior electrostatic control over the channel, reducing short channel effects and leakage while maintaining compatibility with standard fabrication processes through the use of alternating semiconductor layers that can be selectively removed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for uniform scavenging of interfacial layers, reducing the equivalent oxide thickness and tuning the threshold voltage, thereby enhancing device performance and density.
Implementation Method 1
gate stacks using gate dielectric materials having a high dielectric constant (e.g., high-k dielectrics) have been implemented
Implementation Method 2
an interfacial layer may be required between the gate dielectric layer (e.g., HfO2) and the channel
Data Source
AI summary
A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.