Multi-gate FinFET Strain Engineering Parasitic Resistance
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Solution Overview
Problem
Conventional multi-gate transistors face challenges in reducing parasitic contact resistance and enhancing channel mobility, which limits their performance and efficiency.
Innovation Solution
The method involves forming multi-gate fins using a sacrificial gate and barrier layer process, with strain engineering to modulate the transistor channel, reducing parasitic contact resistance and increasing electron/hole mobility by stretching atoms within the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar MOSFET structures are used, then manufacturing is simpler, but parasitic contact resistance increases and channel mobility decreases
Solution Approach 1:
The patent transitions from conventional planar two-dimensional transistor structures to three-dimensional multi-gate FinFET structures. This dimensional change allows the gate to control the channel from multiple directions (top and sidewalls), significantly improving channel mobility and reducing parasitic contact resistance while maintaining manufacturability through established semiconductor fabrication processes adapted for vertical structures.
Solution Approach 2:
The transistor channel is segmented into multiple fins or fingers arranged in a three-dimensional configuration. Each fin acts as an independent channel region controlled by its own gate, allowing parallel conduction paths that reduce overall parasitic resistance while maintaining compact footprint. The segmentation enables better electrical control and heat dissipation.
2Reliability
If multi-gate FinFET structures are implemented, then channel mobility increases and parasitic contact resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary sacrificial gate structures that are formed before the final gate electrode. These sacrificial gates (made of materials like silicon nitride or oxide) define the fin geometry and are removed later to release the multi-gate structure. This preliminary action simplifies the complex self-aligned etching processes required to create the three-dimensional FinFET structure without requiring precise multiple alignment steps.
Solution Approach 2:
Sacrificial gate materials serve as intermediary structures during fabrication. These temporary structures guide the formation of the final multi-gate geometry through self-aligned processes, acting as mediators that simplify the manufacturing of complex three-dimensional structures. The sacrificial gates are eventually removed after serving their structural definition purpose.
3Reliability
If multi-gate FinFET structures are implemented, then parasitic contact resistance decreases, but energy consumption for strain engineering increases
Solution Approach 1:
The patent utilizes strain engineering by modifying physical parameters of the channel material and structure. Tensile or compressive strain is introduced through misfit dislocations in heteroepitaxial layers or through mechanical stress from surrounding structures. This parameter change in the crystal lattice spacing enhances carrier mobility by modifying effective mass and scattering rates, reducing the energy required for charge transport.
Solution Approach 2:
The patent employs composite material structures with different semiconductor layers (e.g., SiGe source/drain regions with silicon channel, or III-V heterostructures). These composite structures naturally generate strain through lattice mismatch, creating built-in stress fields that enhance carrier mobility without requiring external energy input. The strain is inherent to the material composition and structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces energy consumption, operating temperature, and voltage requirements, resulting in improved device performance and robustness.
Implementation Method 1
strain engineering to modulate the transistor channel, reducing parasitic contact resistance and increasing electron/hole mobility by stretching atoms within the channel
Data Source
AI summary
Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.