Multi-Gate FinFET ILD Layer Integrity via Composite Dielectric Etch Selectivity
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating fin-type field effect transistors (FinFETs) due to inter-layer dielectric (ILD) loss during fabrication processes, necessitating an improvement in the manufacturing and operation of FinFETs.
Innovation Solution
A method is developed involving the use of a high etch selectivity material as an inter-layer dielectric (ILD) hard mask layer, where a first ILD layer is deposited and planarized, followed by a second ILD layer with a lower etch rate to prevent loss during the etching process, and a gate stack is formed around fin structures with an etch stop layer and sacrificial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard ILD layer is used during FinFET fabrication, then the fabrication process is simple, but ILD loss occurs during etching processes
Solution Approach 1:
The patent applies composite materials by combining multiple ILD layers with different etch selectivities. A first ILD layer (e.g., silicon oxide) is deposited and planarized, then a second ILD layer with lower etch rate (e.g., silicon nitride or carbon-doped silicon nitride) is deposited over it. This composite structure prevents ILD loss during etching while maintaining fabrication control, resolving the contradiction between reliability and complexity.
2Manufacturing precision
If etching is performed to form gate stacks, then precise gate formation is achieved, but ILD loss occurs
Solution Approach 1:
The patent uses the second ILD layer as an intermediary protective barrier during etching operations. This layer has lower etch selectivity than the first ILD layer, meaning it etches slower and acts as a protective shield during the gate stack formation process. The hard mask layer serves as another intermediary that enables precise patterning while preventing unwanted ILD removal, thus achieving both precision and material preservation.
3Reliability
If ILD loss is prevented using protective layers, then ILD integrity is maintained, but the number of fabrication steps increases
Solution Approach 1:
The patent applies preliminary action by depositing the second ILD layer with lower etch rate before the etching process that forms gate stacks. This preventive measure is taken in advance to protect the first ILD layer from loss during subsequent etching operations. By preparing this protective structure beforehand, the patent prevents ILD loss without requiring additional corrective steps later, thus maintaining productivity while ensuring reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents ILD loss and enhances control over the etching process, improving the fabrication and operation of FinFETs by maintaining the integrity of the ILD layers and allowing for precise formation of gate stacks.
Implementation Method 1
a second ILD layer different from the first ILD layer is deposited over the first ILD layer. The second ILD layer prevents loss of the first ILD layer during the etching process.
Data Source
AI summary
A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.