Multi-Gate FinFET Gate Stack for Threshold Voltage Control
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Solution Overview
Problem
The increasing demand for higher integration density in integrated circuit (IC) devices leads to undesirable short-channel effects (SCE) in transistors, degrading the reliability of IC devices, which existing technologies have not adequately addressed.
Innovation Solution
The implementation of an integrated circuit device with a multi-gate structure, featuring fin-type semiconductor active regions and gate structures with specific material compositions and oxygen content ratios to precisely adjust threshold voltages and improve performance, including the use of metal nitrides, oxides, and oxynitrides in the gate structures to reduce leakage current and enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased through downscaling, then productivity and integration density are improved, but short-channel effects occur degrading reliability
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional multi-gate structures (FINFETs and nanosheet transistors). The channel is formed as vertical fins or stacked nanosheets with gates wrapping around them, providing electrostatic control from multiple directions. This dimensional change enhances gate control over the channel, suppressing short-channel effects while maintaining scaled dimensions for high integration density.
Solution Approach 2:
The patent employs composite material structures in the gate stack, including high-k dielectric materials (such as HfO2, ZrO2) combined with metal gate materials (such as TiN, TaN). This composite gate structure provides both the electrostatic control needed to suppress short-channel effects and the work function tuning capability to adjust threshold voltages, thereby improving transistor reliability at scaled dimensions.
2Reliability
If multi-gate structures are implemented to reduce short-channel effects, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the channel into multiple segmented regions through stacked nanosheets or divided fins, with independent gate control over each segment. This segmentation allows separate threshold voltage tuning for different channel regions, enabling independent optimization of device characteristics while maintaining the benefits of multi-gate control for suppressing short-channel effects.
Solution Approach 2:
The patent implements spatially varying material compositions within the gate structure, such as gradient doping profiles, varying dielectric constants across the gate stack, or composition gradients in metal nitride/oxide/oxynitride layers. This local quality variation enables precise threshold voltage control in different regions of the transistor while maintaining overall structural integrity and reliability.
3Reliability
If material compositions are precisely controlled to adjust threshold voltages, then performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes controllable parameter variations in the gate material stack, including oxygen content gradients, nitrogen content variations, and metal ratio adjustments in metal nitride/oxide/oxynitride compounds. By precisely controlling these compositional parameters during deposition, the threshold voltage can be tuned across a wide range while maintaining manufacturability through standard semiconductor fabrication processes.
Solution Approach 2:
The patent employs composite gate materials with multiple functional layers (metal nitride for adhesion and barrier, metal oxide for dielectric and work function control, metal oxynitride for intermediate properties). Each layer contributes specific properties that collectively enable threshold voltage adjustment, distributing the precision requirement across multiple layers rather than demanding extreme precision from a single material.
Data Source
AI summary
An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.