Multi-gate FinFET Transistor with Pocket Doped Source Region
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional tunneling field effect transistors (TFETs) face challenges with scaling down due to short channel effects (SCE) and drain-induced barrier lowering (DIBL) leakage, which increase power consumption and limit further miniaturization.
Innovation Solution
A multi-gate FinFET device is developed with a fin structure, a gate structure perpendicular to the substrate, and a pocket doped region in the source region, featuring source and drain regions of complementary conductivity types, which enhances on-current (Ion) and reduces turn-on voltage (Von), while suppressing SCE and DIBL leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional planar TFET device is used, then off-state leakage current is reduced, but short channel effect and DIBL leakage increase when scaling down
Solution Approach 1:
The patent transitions from a planar transistor structure to a multi-gate FinFET structure by adding vertical dimensionality. The fin structure extends vertically from the substrate, and multiple gates wrap around the fin, providing control from top, bottom, and sidewalls. This dimensional change enhances gate control over the channel, effectively suppressing short channel effects and DIBL leakage while maintaining low off-state current.
Solution Approach 2:
The patent segments the gate control into multiple independent gates (first gate and second gate) that control different portions of the channel. The first gate controls the first conductivity type carrier flow, while the second gate controls the second conductivity type carrier flow. This segmentation allows independent optimization of threshold voltages and control characteristics for each carrier type, improving overall device performance and suppressing leakage.
2Area of stationary object
If device dimensions are reduced for higher density, then packaging density increases, but power consumption increases due to leakage currents
Solution Approach 1:
By transitioning to a vertical FinFET structure, the patent achieves higher packaging density through increased vertical integration while the multi-gate configuration provides superior electrostatic control that reduces leakage currents. This allows continued scaling without the exponential increase in power consumption that plagues conventional planar devices.
Solution Approach 2:
The patent employs pocket doped regions with specific conductivity types to modify the electrical parameters of the source and drain regions. These doped regions adjust carrier concentrations and energy band structures, optimizing the balance between on-state current and off-state leakage, thereby reducing power consumption while maintaining high density.
3Reliability
If multi-gate FinFET structure is implemented, then SCE and DIBL leakage are suppressed, but device complexity increases
Solution Approach 1:
While the vertical FinFET structure adds dimensional complexity, it actually simplifies the fabrication process by using standard semiconductor manufacturing techniques adapted for vertical structures. The multi-gate configuration, though structurally complex, provides unified control mechanisms that simplify threshold voltage adjustment and leakage suppression compared to multiple separate planar devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-gate FinFET device achieves improved on-current and lower turn-on voltage, enabling effective scaling down and reducing power consumption by mitigating SCE and DIBL leakage, thus overcoming the limitations of conventional planar transistors.
Implementation Method 1
a green fin field effect transistor (FinFET) device based on quantum mechanical tunneling effect
Data Source
AI summary
A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other.