Multi-Gate NAND Flash Transistors for High Breakdown in Small Footprints
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Solution Overview
Problem
Conventional transistors used in NAND flash memory devices require high breakdown voltages and large footprints, necessitating overdrive voltages for effective operation, which can be inefficient and limit memory density.
Innovation Solution
The use of multi-gate transistors with multiple independent control gates surrounding an active area, allowing for more efficient voltage distribution and reduced transistor size, thereby enabling higher breakdown voltages without the need for excessive overdrive voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors with high breakdown voltages are used, then reliability is improved, but area increases
Solution Approach 1:
The transistor gate is divided into multiple independent gates (first gate, second gate, third gate) that can be independently controlled. This segmentation allows each gate to handle a portion of the voltage stress, enabling high breakdown voltage operation without proportionally increasing the transistor footprint, as the gates share the voltage blocking function.
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing multiple gates at different heights (first gate at lower level, second and third gates at upper levels). This three-dimensional gate arrangement increases the effective gate control volume without proportionally increasing the planar footprint, allowing high voltage operation in a compact area.
2Reliability
If overdrive voltages are applied to achieve high breakdown voltages, then reliability is improved, but energy consumption increases
Solution Approach 1:
The multiple independent gates can be selectively activated based on operating conditions. During high-voltage operations, all gates can be engaged to provide maximum breakdown protection. During normal low-voltage operations, fewer gates need to be active, reducing the overdrive voltage requirements and associated power consumption while maintaining adequate reliability.
Solution Approach 2:
The patent enables dynamic control of gate voltages where the first, second, and third gates can be independently biased. This allows the system to adaptively apply overdrive voltages only when and where needed for breakdown protection, rather than continuously applying high overdrive voltages across all gates, thereby reducing overall energy consumption while maintaining reliability.
Data Source
AI summary
Transistors, and memories including such transistors, might include an active area having a first conductivity type, first and second source/drain regions in the active area and having a second conductivity type, and a plurality of control gates between the first and second source/drain regions and the second source/drain region, wherein each control gate of the plurality of control gates includes a respective first control gate portion overlying a first side of the active area, and a respective second control gate portion connected to its respective first control gate portion that is either adjacent to a second side of the active area orthogonal to the first side of the active area, or underlying a second side of the active area opposite the first side of the active area.