Multi-Gate GaN Transistor Layout for Compact ESD Protection
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Solution Overview
Problem
Existing GaN-based high frequency devices are vulnerable to electrostatic discharge (ESD) breakdown, and existing electrostatic protection circuits occupy a large area, necessitating a solution that enhances ESD protection while minimizing space.
Innovation Solution
A multi-gate transistor structure is employed, where multiple field effect transistors share main electrodes and are electrically coupled in series, integrated with a resistor, to distribute electrostatic discharge voltage and reduce the occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple MOS transistors are separated by device isolation to improve electrostatic breakdown voltage, then electrostatic protection is enhanced, but the occupied area increases
Solution Approach 1:
The patent merges multiple MOS transistors into a shared structure where adjacent transistors share common device isolation regions and electrode connections. This combining approach maintains the voltage division protection mechanism while eliminating redundant isolation structures, thereby reducing the total occupied area while preserving electrostatic breakdown protection.
Solution Approach 2:
The shared device isolation regions serve multiple adjacent transistors simultaneously, making the isolation structure multi-functional. This universal approach allows a single isolation region to protect multiple transistor gates, reducing the overall number of isolation regions needed and consequently decreasing the occupied area while maintaining comprehensive electrostatic protection.
2Reliability
If the number of MOS transistor connections is increased to improve electrostatic protection, then breakdown voltage resistance is enhanced, but device complexity increases
Solution Approach 1:
Adjacent MOS transistors share common source and drain electrodes, as well as common device isolation regions. This merging of electrical connections reduces the total number of discrete connections required while maintaining the voltage division mechanism across multiple transistors, thereby enhancing electrostatic protection without proportionally increasing device complexity.
Data Source
AI summary
A semiconductor device includes a multi-gate transistor, a first terminal, and a second terminal. The multi-gate transistor includes field effect transistors that each have a pair of main electrodes and a gate electrode disposed between the pair of main electrodes and that are electrically coupled in series while sharing the main electrodes. The first terminal is electrically coupled to one of the main electrodes of the field effect transistor at one end of the series-coupled field effect transistors of the multi-gate transistor, and receives or outputs a signal. The second terminal is electrically coupled to another of the main electrodes of the field effect transistor at another end of the series-coupled field effect transistors of the multi-gate transistor and receives supply of a fixed potential. The gate electrode of at least one of the field effect transistors of the multi-gate transistor is electrically coupled to the other main electrode of the same field effect transistor.