Multi-Gate Gate Structure Fill to Eliminate Seams and Voids
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of gate structures in multi-gate transistors, such as FinFETs and MBC transistors, is challenged by the difficulty in creating seamless gate structures without voids or seams, which can lead to unevenness and increased contact resistance during gate recess processes.
Innovation Solution
A process involving atomic layer deposition (ALD) of a nanocrystalline metal nitride layer with controlled grain size is used to form a metal fill layer, followed by nitrogen plasma treatment, ensuring the gate structure is free of middle seams and allows for anisotropic etching, resulting in improved gap fill performance and reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate structures are formed for multi-gate transistors, then gate control is improved by increasing gate-channel coupling, but seams or voids may form causing unevenness during gate recess processes
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer (CMP process) before the gate recess process to pre-compensate for any potential unevenness. This preliminary planarization ensures that subsequent etching processes work on a uniform surface, preventing the formation of seams or voids during gate recess while maintaining the multi-gate structure's control benefits
2Reliability
If gate structure extends vertically to wrap over fin or plurality of nanostructures, then gate-channel coupling is increased, but it becomes challenging to form gate structure without seams or voids
Solution Approach 1:
The patent segments the gate structure formation into distinct layers: a first gate electrode layer, a second gate electrode layer, and an insulating layer between them. This segmentation allows each layer to be formed and planarized independently, simplifying the overall process and enabling seamless vertical extension around fins and nanostructures without seams or voids
3Ease of manufacture
If existing gate structures are used, then general purposes are satisfied, but unevenness occurs when subjected to gate recess processes
Solution Approach 1:
The patent changes the physical parameters of the gate structure by introducing a planarization layer and controlling the thickness and material properties of the insulating layer. These parameter changes ensure that the gate structure maintains uniform surface topology even when subjected to gate recess processes, while preserving general manufacturability across different device configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures seamless gate structures with suppressed lateral etching, enhancing conductivity and reducing contact resistance, thereby improving the manufacturing efficiency and performance of multi-gate transistors.
Implementation Method 1
A process involving atomic layer deposition (ALD) of a nanocrystalline metal nitride layer with controlled grain size is used to form a metal fill layer
Implementation Method 2
followed by nitrogen plasma treatment, ensuring the gate structure is free of middle seams and allows for anisotropic etching
Data Source
AI summary
A method according to the present disclosure includes providing a substrate that includes a dummy gate stack wrapping over an active region, and a spacer layer extending along sidewalls of the dummy gate stack, selectively removing the dummy gate stack to form a gate trench exposing the active region, depositing a gate dielectric over the active region, depositing at least one work function layer over the gate dielectric layer, depositing a tungsten layer over the at least one work function layer, and depositing a tungsten nitride layer over the tungsten layer.