Multigate Gate Profile Tuning to Prevent Void and Seam Formation
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Solution Overview
Problem
As IC feature sizes shrink, gate replacement processes face challenges with void and seam formation in multigate devices due to high aspect ratios of gate openings, leading to degraded performance and reduced device yield.
Innovation Solution
The method involves modifying the gate profile by partially removing the dummy gate and treating the gate spacers through ion-dominated or radical-dominated oxidation to enlarge the gate opening width, reducing the aspect ratio and preventing pinch-off during the gate stack fill process, thereby minimizing void and seam formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate replacement processes are used to improve device performance, then threshold voltage control is improved, but void and seam formation occurs in multigate devices due to high aspect ratios
Solution Approach 1:
The patent applies preliminary action by performing gate profile modification before the gate stack fill process. Specifically, the dummy gate is partially removed and gate spacers are treated to enlarge the gate opening width at controlled heights, creating a more favorable geometry for subsequent material deposition. This preliminary geometric adjustment prevents pinch-off during filling and reduces void/seam formation, thereby resolving the contradiction between achieving good device performance and avoiding manufacturing defects.
Solution Approach 2:
The patent implements local quality by selectively modifying the gate profile at specific heights rather than uniformly throughout. The gate opening width is enlarged at predetermined heights (e.g., above the channel layer) while maintaining the original profile in other regions. This localized modification optimizes the fill process where needed without altering the overall device structure, allowing threshold voltage control to be maintained while preventing void and seam formation.
2Manufacturing precision
If gate opening width is enlarged to reduce aspect ratio, then void and seam formation is reduced, but critical dimensions may be compromised
Solution Approach 1:
The patent uses preliminary action to adjust the gate opening geometry before filling, creating a tapered or enlarged profile at specific heights that facilitates complete material deposition. This preliminary geometric modification ensures that the final gate stack achieves the desired critical dimensions without voids or seams, as the optimized profile allows uniform filling while maintaining precise dimensional control through controlled enlargement at predetermined heights.
Solution Approach 2:
The patent applies parameter changes by modifying the gate opening width at controlled heights through selective dummy gate removal and gate spacer treatment. This controlled parameter adjustment enlarges the opening where needed to prevent pinch-off and void formation, while the treatment parameters (oxidation type, duration, conditions) are optimized to maintain the correct final critical dimensions after gate stack formation, thus resolving the contradiction between reducing defects and preserving dimensional accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the gate stack fill process window, reduces void and seam formation, and enhances device performance by ensuring a more uniform and complete filling of the gate stack, maintaining desired critical dimensions and increasing device yield.
Implementation Method 1
treating the gate spacers through ion-dominated or radical-dominated oxidation to enlarge the gate opening width
Implementation Method 2
treating the gate spacers through ion-dominated or radical-dominated oxidation to enlarge the gate opening width
Data Source
AI summary
Gate profile tuning techniques are disclosed herein. An exemplary gate profile tuning method includes forming a gate structure over a channel layer. The gate structure includes a dummy gate and gate spacers disposed along sidewalls of the dummy gate. The method further includes partially removing the dummy gate to form a gate opening that defines a gate profile. The gate profile is then modified by treating portions of the gate spacers (for example, by oxygen plasma treatment) and removing the treated portions of the gate spacers (for example, by oxide removal). After removing a remainder of the dummy gate to expose the channel layer, a gate stack of the gate structure is formed in the gate opening. The gate stack has a funnel-shaped profile. In some embodiments, a width of the gate stack above the channel layer is greater than a width of the gate stack below the channel layer.