Multi-Gate Gate Stack Sealing for Void-Free Replacement Gates
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Solution Overview
Problem
The integration of gate-all-around (GAA) devices faces challenges in void formation during the replacement gate process due to shrinking dimensions and limited gap filling capability, leading to impurity introduction and transistor performance degradation.
Innovation Solution
A blocking layer is formed above the work function metal layer to seal voids and improve adhesion, preventing impurity entry and enhancing transistor performance by maintaining uniform WFM resistance and threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistor dimensions are scaled down to sub-10 nm nodes, then gate control and mitigation of short-channel effects are improved, but void formation occurs during replacement gate process due to limited gap filling capability
Solution Approach 1:
The work function metal layer is deposited conformally around the channel members before the gap is fully closed, establishing a preliminary structure that will later be selectively removed. This preliminary deposition allows the metal to wrap around the channel members during subsequent gap closure, ensuring complete coverage while maintaining control over the final gap filling process
Solution Approach 2:
The gap filling process is segmented into multiple stages: first conformal deposition of work function metal, then selective removal of metal in non-gap regions, followed by final gap filling with different materials. This segmentation allows different materials to be deposited in different regions at different times, preventing void formation while maintaining gate control
2Reliability
If work function metal layer is deposited to wrap around channel members, then gate-all-around control is achieved, but impurities enter through voids causing resistance and threshold voltage shifts
Solution Approach 1:
The work function metal layer is selectively removed from regions outside the gap between channel members, extracting the metal only where it is not needed. This leaves the metal intact around the channel members for gate control while eliminating potential impurity sources from excess metal regions
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the work function metal layer and the final gap filling material. This intermediary layer seals the gap region, preventing impurities from entering through voids while allowing the work function metal to maintain its gate-all-around control function
3Ease of manufacture
If conventional gap filling methods are used, then manufacturing process is simple, but adhesion between layers is insufficient and performance is degraded
Solution Approach 1:
Different materials and deposition methods are applied to different regions: conformal deposition for work function metal around channel members, selective removal in non-gap regions, and targeted gap filling with adhesion-optimized materials. This local differentiation improves adhesion where critical while maintaining manufacturing simplicity in less critical regions
Data Source
AI summary
A method of manufacturing a semiconductor device includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first and second semiconductor layers into a fin structure, forming a dielectric layer across the fin structure, and removing the first semiconductor layers of the fin structure thereby forming gaps between the second semiconductor layers of the fin structure. The method also includes depositing a first metal layer to wrap around the second semiconductor layers thereby forming voids between opposing sidewalls of the dielectric layer, recessing the first metal layer, forming a blocking layer over the recessed first metal layer thereby covering the voids, and depositing a second metal layer over the blocking layer.