Engineered Multigate Gate Stack for GAA Channel Control
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Solution Overview
Problem
Challenges in fabricating gate structures for gate-all-around (GAA) devices have degraded device performance and increased processing complexity, hindering the advancement of integrated circuit manufacturing.
Innovation Solution
A method for fabricating multigate devices, including GAA transistors, involves forming semiconductor layers with nonuniform composition and patterning them to create fins with specific profiles, followed by the formation of gate structures that extend around the channels, optimizing source/drain features for reduced parasitic capacitance and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate structures are used for GAA devices, then fabrication process complexity increases and device performance degrades
Solution Approach 1:
The patent applies preliminary action by forming the gate structure before the source/drain regions in the fabrication sequence. This reverse ordering compared to conventional processes allows the gate to serve as a template that defines the subsequent source/drain formation, thereby simplifying the overall fabrication process while improving device performance through better gate control
Solution Approach 2:
The gate structure is segmented into multiple components including a gate dielectric layer, a gate electrode layer, and an optional capping layer. This segmentation allows each layer to be optimized independently for its specific function, improving device performance while maintaining fabrication simplicity through standardized layer-by-layer deposition processes
2Manufacturing precision
If gate structures are optimized for better control, then manufacturing complexity increases
Solution Approach 1:
The gate structure design serves multiple functions simultaneously: the gate dielectric provides electrical isolation, the gate electrode provides control, and the overall structure serves as a template for source/drain formation. This multi-functionality achieves better gate control without increasing manufacturing complexity, as the same structure performs multiple roles in the device operation and fabrication process
3Use of energy by moving object
If source/drain features are optimized for reduced parasitic capacitance, then contact resistance may increase
Solution Approach 1:
The source/drain regions are engineered with local quality variations, including lightly-doped extension regions adjacent to the gate and heavily-doped contact regions at the terminals. This spatial variation in doping concentration reduces parasitic capacitance in the gate overlap region while maintaining low contact resistance at the contact points, simultaneously addressing both parameters
Data Source
AI summary
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate; a gate stack disposed on the fin region, wherein the gate stack is wrapping around each of the multiple channels and includes gate extensions being extending laterally to be overlapped with inner spacers; and a pair of source/drain (S/D) features formed on the fin region, interposed by the gate stack, and connected with the multihple channels.