Multigate Gate Stack Layout for Oxygen and Threshold Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multigate device fabrication methods face challenges in forming gate stacks due to unintentional oxidation of layers, leading to performance degradations such as slower device speed and threshold voltage variations, particularly in IC applications like SRAM devices, where n-type transistor performance is critical.
Innovation Solution
A gate stack configuration that omits a cap from inner regions, varies the thickness of the work function layer between inner and outer regions, and lowers aluminum content to reduce oxygen differences, thereby improving device reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cap is included in inner regions of the gate stack, then oxidation protection is provided, but oxygen differences and threshold voltage variations increase
Solution Approach 1:
The patent removes the cap layer from inner regions of the gate stack, extracting the source of oxygen that causes threshold voltage variations. This selective removal eliminates the harmful oxygen diffusion path while preserving the beneficial oxidation protection in outer regions, directly resolving the contradiction between oxidation protection and threshold voltage control.
Solution Approach 2:
The gate stack is designed with different structures in different regions: outer regions include the cap for oxidation protection, while inner regions omit the cap to prevent oxygen-induced threshold voltage variations. This local differentiation allows each region to optimize its function, resolving the contradiction between uniform oxidation protection and localized threshold voltage control.
2Reliability
If the work function layer thickness is increased to fill spaces between channel layers, then gate control is improved, but oxygen diffusion and threshold voltage variations worsen
Solution Approach 1:
The patent removes the cap from inner regions where oxygen diffusion occurs, eliminating the source of threshold voltage variations. This allows the work function layer to be thicker and fill spaces between channel layers for improved gate control, without the harmful effect of oxygen diffusion through the cap layer.
Solution Approach 2:
The work function layer is designed with varying thickness: thicker in inner regions to fill spaces between channel layers and improve gate control, and thinner in outer regions where the cap provides oxidation protection. This local differentiation resolves the contradiction between gate control and threshold voltage stability.
3Productivity
If device feature sizes are decreased for scaling, then device density is improved, but gate stack volume reduction causes gate layers to fill gate openings, limiting fine tuning capability
Solution Approach 1:
The gate stack uses different layer configurations in different regions: inner regions have thicker work function layers for gate control, while outer regions have thinner layers. This local differentiation allows the gate stack to maintain fine tuning capability despite overall volume reduction from device scaling, resolving the contradiction between device density and configuration flexibility.
Data Source
AI summary
An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and/or surrounds a first semiconductor layer disposed over a second semiconductor layer. The gate dielectric and the work function layer (and not the cap and/or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. A thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.