Multi-Gate Transistor Gate Stack Without Inner Spacer Defects
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Solution Overview
Problem
Current methods for fabricating multi-gate devices, such as FinFETs and GAA transistors, face challenges with inner spacer formation, including defects and voids in the source/drain epitaxial layer, which affect device performance and complexity.
Innovation Solution
The proposed solution involves a process flow that merges the interfacial layer (IL) and high-K dielectric (HK) layers between nanowires, eliminating the need for an inner spacer, thereby simplifying the fabrication process and enhancing device performance by directly forming a gate structure over the merged IL/HK layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inner spacer layer is formed between nanowires to define gate regions, then gate structure formation is enabled, but defects and voids appear in the source/drain epitaxial layer
Solution Approach 1:
The patent removes the inner spacer layer entirely from the fabrication process. Instead of forming an inner spacer between nanowires to define gate regions, the process directly forms the gate structure over the merged IL/HK layers, eliminating the source of defects and voids in the source/drain epitaxial layer while still achieving proper gate region definition through the merged dielectric layers
2Manufacturing precision
If a dedicated inner spacer layer is used to define gate regions, then precise gate positioning is achieved, but fabrication process complexity increases
Solution Approach 1:
The patent merges the interfacial layer (IL) and high-K dielectric (HK) layers into a single combined dielectric structure that performs the function previously requiring a separate inner spacer layer. This merging eliminates additional fabrication steps while maintaining precise gate region positioning through the integrated dielectric structure that defines the gate boundaries
Solution Approach 2:
The merged IL/HK dielectric structure serves multiple functions simultaneously: it provides electrical isolation, defines gate region boundaries, and serves as the gate insulator substrate. This multi-functional structure replaces what previously required separate dedicated spacer layers and additional process steps
3Shape
If conventional FinFET or GAA fabrication processes are used, then multi-gate device structure is achieved, but inner spacer defects reduce device performance
Solution Approach 1:
The patent converts the potential harm of complex spacer formation processes into a benefit by eliminating the spacer layer entirely. The direct formation of gate structures over merged IL/HK layers without inner spacers prevents defect formation while maintaining the desired multi-gate device geometry, thereby improving device performance through a simplified process
Data Source
AI summary
A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.