Multigate Gate Stack With In-Situ Tungsten for Low Resistance
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Solution Overview
Problem
Conventional multigate device fabrication methods face challenges in scaling device dimensions, leading to reduced gate stack volume, increased gate resistance, and susceptibility to oxidation, which affects device performance and threshold voltage variability.
Innovation Solution
A gate stack fabrication method involving an in-situ fluorine-free tungsten layer deposition over a silicon-comprising capping layer, combined with a low aluminum content work function layer, to reduce gate resistance and inhibit oxidation, using co-flowing tungsten and hydrogen precursors to enhance deposition and growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate opening dimensions are decreased to scale down device feature sizes, then device integration density is improved, but gate stack volume is reduced leaving limited room for fine tuning threshold voltage
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap around the channel region. This dimensional change provides additional spatial dimensions for gate layer configuration, enabling multiple work function layers and thicker layers to be accommodated even in scaled devices, thus resolving the contradiction between integration density and configuration flexibility
Solution Approach 2:
The patent implements a nested multi-layer gate structure where different functional layers (gate dielectric, work function layers, conductive layers) are stacked and wrapped around the channel. This nesting approach allows multiple threshold voltage tuning layers to be integrated within the confined gate opening volume, maintaining fine-tuning capability while scaling down device dimensions
2Manufacturing precision
If gate layers are made thicker to enable fine tuning of threshold voltage, then threshold voltage control is improved, but gate opening fills up leaving no room for additional layers
Solution Approach 1:
By adopting gate-all-around structures that extend vertically and wrap around the channel, the patent utilizes the third dimension (vertical height) to accommodate thicker gate layers. This allows sufficient thickness for voltage tuning while maintaining horizontal scaling, resolving the volume conflict
Solution Approach 2:
The patent employs composite gate structures combining multiple materials with different functions - gate dielectric materials, work function materials, and conductive materials - in layered configurations. This composite approach enables thick functional layers for voltage control while optimizing space utilization through material-specific placement strategies
3Manufacturing precision
If conventional gate replacement process is used with multiple work function layers, then threshold voltage tuning capability is improved, but gate resistance increases affecting device speed
Solution Approach 1:
The patent applies different material properties to different regions of the gate structure - using low-resistance conductive materials in regions where current flows and work function materials where voltage control is needed. This local optimization reduces overall gate resistance while preserving threshold voltage tuning capability through strategic material placement
Solution Approach 2:
The gate electrode structure combines multiple materials with complementary properties - work function materials for voltage control and low-resistance conductive materials for current transport. This composite construction achieves both threshold voltage tuning and low gate resistance, resolving the contradiction between precision and speed
4Ease of manufacture
If gate stack layers are exposed to oxidation environment, then fabrication process flexibility is improved, but gate stack becomes susceptible to oxidation affecting device performance
Solution Approach 1:
The patent employs inert or reducing atmosphere processing during gate stack fabrication to prevent oxidation of sensitive layers. By maintaining controlled atmospheric conditions throughout the fabrication process, the patent achieves both fabrication flexibility and oxidation resistance, resolving the contradiction between ease of manufacture and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method results in lower gate resistance, improving device speed and reducing threshold voltage variation, particularly beneficial for IC applications like ring oscillators.
Implementation Method 1
forming a fluorine-free tungsten layer over a silicon-comprising capping layer... The fluorine-free tungsten layer is formed over the silicon-comprising layer by co-flowing a tungsten-comprising precursor and a hydrogen-comprising precursor
Data Source
AI summary
An exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric over a channel layer and forming a gate electrode over the gate dielectric. Forming the gate electrode includes forming a work function layer over the gate dielectric and forming a cap over the work function layer. Forming the cap includes forming a metal nitride layer over the work function layer and forming a silicon-comprising layer over the metal nitride layer. Forming the gate electrode includes forming a fluorine-free tungsten layer over the silicon-comprising layer of the cap without breaking vacuum. Forming the fluorine-free tungsten layer over the silicon-comprising layer includes co-flowing a tungsten-comprising precursor (e.g., WCl5) and a hydrogen-comprising precursor (e.g., H2).