Multigate Gate Stack Layout for Threshold Voltage Tuning
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Solution Overview
Problem
As IC technology nodes continue to scale, fabricating gate stacks around a channel region of a multigate device becomes challenging due to decreasing device feature sizes, leading to reduced gate stack volume and limited room for fine-tuning threshold voltage.
Innovation Solution
A gate stack configuration that omits a cap in inner regions, configures a work function layer with different thicknesses in inner and outer regions, and lowers the aluminum content of the work function layer, thereby reducing oxygen differences between inner and outer regions of the gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device feature sizes are decreased to enable scaling, then device density and integration are improved, but gate stack volume is reduced and threshold voltage fine-tuning capability is lost
Solution Approach 1:
The gate stack employs different aluminum content levels in different regions of the work function layer. The inner regions (between channel layers) have lower aluminum content while outer regions have higher aluminum content, allowing localized threshold voltage adjustment without increasing overall gate stack volume. This regional differentiation enables fine-tuning capability despite scaled dimensions.
2Length of moving object
If gate stack volume is reduced due to scaling, then device feature sizes are decreased, but room for threshold voltage fine-tuning is limited
Solution Approach 1:
The invention changes the aluminum content parameter within the work function layer to achieve threshold voltage fine-tuning. By varying aluminum concentration from 0-50 at% in inner regions to 30-70 at% in outer regions, the gate stack achieves multiple threshold voltage states without requiring additional physical space or increased gate stack volume.
3Manufacturing precision
If work function layer thickness is increased to enable threshold voltage tuning, then threshold voltage control is improved, but gate resistance increases
Solution Approach 1:
The work function layer has non-uniform aluminum content distribution with thinner, lower-aluminum inner regions for threshold voltage control and thicker, higher-aluminum outer regions for low resistance. This spatial variation in composition allows simultaneous optimization of both threshold voltage precision and gate resistance without compromise.
4Object-affected harmful factors
If cap is added to gate stack to protect from oxidation, then oxidation protection is improved, but oxygen differences between inner and outer regions increase
Solution Approach 1:
The aluminum content in the work function layer is specifically optimized to compensate for oxygen diffusion effects. Lower aluminum content in inner regions (0-50 at%) and higher content in outer regions (30-70 at%) creates a compositional gradient that balances oxygen distribution throughout the gate stack, maintaining compositional stability despite cap protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves device reliability and performance by reducing threshold voltage variations and increasing device speed, while also reducing gate resistance and minimizing unintended oxidation.
Implementation Method 1
outer regions of the gate stack have a greater amount of oxygen than inner regions of the gate stack... lowers the aluminum content of the work function layer... reducing oxygen differences between inner and outer regions of the gate stack
Data Source
AI summary
An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and/or surrounds a first semiconductor layer disposed over a second semiconductor layer. The gate dielectric and the work function layer (and not the cap and/or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. A thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.