Multi-Gate Inner Spacer Formation for Precise Gate Control
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Solution Overview
Problem
Existing multi-gate device fabrication techniques face challenges in scaling down semiconductor IC dimensions, particularly in forming gate structures around channel regions, leading to unsatisfactory performance and complexity in processing and manufacturing.
Innovation Solution
A method involving the formation of inner spacer features through controlled etching of dummy layers around channel members in multi-gate devices, using a combination of thermal operations and selective etching to define precise inner spacer profiles, which enhances the gate structure's performance by modifying the etch resistance of dummy layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate device fabrication techniques are used to improve gate control, then gate-channel coupling is increased and off-state current is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The method performs preliminary actions by forming inner spacer features and modifying dummy layer etch resistance before gate structure formation. This prepares the structure in advance to enable precise gate patterning and control during subsequent processing steps, resolving the contradiction between improved gate control and fabrication complexity.
Solution Approach 2:
The patent applies local quality by creating distinct regions with different etch resistance properties through thermal operations on dummy layers. Different portions of the structure receive different thermal treatments to achieve localized etch resistance modifications, enabling precise control of inner spacer formation while managing overall device complexity.
2Manufacturing precision
If inner spacer profiles are controlled through selective etching to improve gate structure performance, then gate control is enhanced, but processing complexity increases
Solution Approach 1:
The patent changes physical parameters by applying thermal operations to modify the etch resistance of dummy layers. By controlling temperature parameters during thermal processing, the method achieves precise control over inner spacer profile formation through selective etching, balancing manufacturing precision with processing complexity.
Solution Approach 2:
The dummy layers serve as intermediary elements that mediate between the fabrication process and the final gate structure. These intermediate layers are selectively modified through thermal operations and removed after serving their purpose in defining inner spacer profiles, enabling precise control without permanently increasing device complexity.
3Manufacturing precision
If dummy layer etch resistance is modified through thermal operations to define precise inner spacer profiles, then manufacturing precision is improved, but energy consumption and process time increase
Solution Approach 1:
The patent applies partial action by performing thermal operations selectively on specific dummy layer regions rather than uniformly across the entire structure. This localized thermal treatment achieves the necessary etch resistance modification for precise inner spacer profile definition while minimizing overall energy consumption and process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the overall performance of semiconductor devices by controlling the inner spacer profiles, thereby improving gate control and reducing off-state current and short-channel effects.
Implementation Method 1
performing a thermal operation to the workpiece, wherein the thermal operation modifies an etch resistance of the first dummy layer
Data Source
AI summary
A method includes providing a workpiece. The workpiece includes a stack of channel layers and sacrificial layers, a dummy gate structure disposed over the stack, and a source/drain trench adjacent to the stack and the dummy gate structure. The method further includes replacing the sacrificial layers with a first dummy layer and a second dummy layer. The second dummy layer is spaced apart from the channel layers by the first dummy layer. The method further includes selectively and partially recessing the first dummy layer and the second dummy layer to form inner spacer recesses among the channel layers, forming inner spacer features in the inner spacer recesses, forming a source/drain feature in the source/drain trench, and replacing the dummy gate structure, the first dummy layer, and the second dummy layer with a metal gate structure.