Multi-Gate Inner Spacer Layers for Etch Resistance and Low Capacitance
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Solution Overview
Problem
Conventional inner spacer features in multi-bridge-channel transistors face challenges in achieving sufficient etch resistance while maintaining a low dielectric constant, leading to potential damage to source/drain features and increased parasitic capacitance due to high dielectric constant materials.
Innovation Solution
The implementation of inner spacer features comprising an outer layer with a higher dielectric constant and an inner layer with a lower dielectric constant, made of silicon, carbon, oxygen, and nitrogen, where the outer layer is etched away to reduce parasitic capacitance and prevent damage during the sacrificial layer removal process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inner spacer features are made with etch resistant dielectric material, then etch resistance is improved, but dielectric constant increases leading to higher parasitic capacitance
Solution Approach 1:
The inner spacer feature is divided into two distinct layers: a first inner spacer layer with high etch resistance and a second inner spacer layer with low dielectric constant. This segmentation allows each layer to perform its specialized function independently, resolving the contradiction between etch resistance and parasitic capacitance.
Solution Approach 2:
The inner spacer feature combines two different dielectric materials with complementary properties - one optimized for etch resistance and the other for low dielectric constant. This composite structure achieves both requirements simultaneously that cannot be met by a single material.
2Reliability
If inner spacer feature thickness is increased to improve etch resistance, then source/drain feature protection is improved, but parasitic capacitance increases
Solution Approach 1:
The thickness requirement is segmented between two layers: the first layer provides the necessary thickness for etch resistance and protection, while the second layer provides the low dielectric constant property. This segmentation allows the protective function and electrical performance function to be decoupled.
Solution Approach 2:
Different regions of the inner spacer feature have different material properties optimized for different functions. The portion requiring etch resistance has high resistance material, while the portion affecting capacitance has low dielectric constant material, achieving local optimization of both properties.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.