Multi-Gate Fin Layout With Self-Aligned Isolation for CPP Scaling
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in scaling down cell height and contacted poly pitch (CPP) due to poor pattern alignment and degraded critical dimension uniformity in photolithography-based metal gate and active region isolation processes, limiting device performance and density.
Innovation Solution
Implementing a self-aligned active region and self-aligned metal gate isolation scheme using dielectric layers and high-k dielectric materials to achieve precise alignment and improved isolation, allowing for reduced cell height and CPP scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used for metal gate and active region isolation, then device isolation is achieved, but pattern alignment precision and critical dimension uniformity deteriorate
Solution Approach 1:
The patent employs self-aligned processes where the metal gate isolation and active region isolation are automatically aligned to each other without requiring additional photolithography alignment steps. The isolation structures are formed using the metal gate pattern itself as the alignment reference, eliminating overlay errors and achieving precise pattern alignment.
Solution Approach 2:
The patent introduces dielectric layers as intermediary materials between the metal gate and the substrate, and between adjacent active regions. These dielectric layers serve as isolation structures that are conformally deposited and then planarized, providing precise dimensional control and uniformity without relying on photolithography patterning.
2Length of moving object
If photolithography process is used for active region isolation, then device isolation is achieved, but device scaling capability deteriorates
Solution Approach 1:
The patent replaces the photolithography-based mechanical patterning system with a deposition-based isolation formation process. Instead of using light patterns to define isolation regions, the patent uses conformal dielectric deposition followed by planarization to create isolation structures with precise dimensional control that is not limited by photolithography resolution.
3Productivity
If conventional isolation processes are used, then device fabrication is simplified, but device density deteriorates
Solution Approach 1:
The patent merges the metal gate isolation process and the active region isolation process into a single integrated flow. Both isolation structures are formed using the same dielectric deposition and planarization steps, eliminating the need for separate photolithography processes and reducing overall process complexity while achieving higher device density.
Data Source
AI summary
A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.