Multi-Gate Isolation Structure for Uniform Gate Cut Profiles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is to form region isolation features and gate cut features that ensure uniform profiles and prevent uneven etching, which can lead to variations in gate structures, threshold voltage, and switching characteristics.
Innovation Solution
The proposed solution involves forming region isolation features before replacing the dummy gate stack with a high-k metal gate structure, ensuring that the gate dielectric layer does not extend along the sidewalls of these features. Gate cut features are then formed after the high-k metal gate structure is in place, without etching the gate dielectric layer along the sidewalls of the region isolation features, to maintain uniformity and prevent uneven etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If region isolation features are formed after replacing dummy gate stack with high-k metal gate structure, then manufacturing sequence is simplified, but gate cut features exhibit uneven profiles and cause variations in gate structures
Solution Approach 1:
The region isolation features are formed in advance, before the dummy gate stack is replaced with the high-k metal gate structure. This preliminary formation ensures that the gate dielectric layer does not extend along the sidewalls of the region isolation features, preventing uneven etching of gate cut features and ensuring uniform profiles while maintaining manufacturing feasibility
2Reliability
If gate dielectric layer extends along sidewalls of region isolation features, then region isolation is achieved, but uneven etching occurs during gate cut feature formation
Solution Approach 1:
Region isolation features are formed preliminarily before gate structure formation, ensuring proper isolation without gate dielectric extension on sidewalls
Solution Approach 2:
The gate dielectric layer is intentionally prevented from extending along the sidewalls of region isolation features, creating a local quality difference that prevents uneven etching while maintaining isolation effectiveness in the region between fins
3Productivity
If manufacturing process is simplified, then productivity increases, but variations in threshold voltage and switching characteristics occur
Solution Approach 1:
Region isolation features are formed in advance before gate structure formation, enabling subsequent gate cut features to be etched uniformly without variations that would affect threshold voltage and switching characteristics, thus maintaining both productivity and precision
Data Source
AI summary
A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin arising from the substrate, an isolation structure disposed between the first base fin and the second base fin, first channel members disposed over the first base fin, second channel members disposed over the second base fin, a region isolation feature extending into the substrate, a first gate structure wrapping around each of the first channel members, second gate structure wrapping around each of the second channel members, a first gate cut feature extending through the first gate structure and into the isolation feature, and a second gate cut feature extending though the second gate structure and into the isolation feature. Each of the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature.