Multi-Gate IC Layout for Separated FinFET and GAA Cells
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Solution Overview
Problem
The integration of different multi-gate devices, such as FinFETs and GAA transistors, on a single integrated circuit is challenging due to dimensional differences, leading to processing issues like oxidation problems, which affect the performance and manufacturing efficiency of nanowire and nanosheet devices.
Innovation Solution
A semiconductor device layout is proposed that combines Nanowire, Nanosheet, and FinFET transistors on a single chip, with specific layout options and isolation structures to optimize gate control and reduce leakage, allowing for flexible design for speed and power optimization, and includes separate regions for FinFETs and GAA transistors with distinct gate lengths and dielectric thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different multi-gate devices (FinFETs and GAA transistors) are integrated on a single integrated circuit, then device performance and design flexibility are improved, but processing complexity and manufacturing difficulty increase due to dimensional differences
Solution Approach 1:
The integrated circuit is divided into separate first and second regions, where the first region contains FinFET devices and the second region contains GAA transistors. This spatial segmentation allows each device type to be processed independently with its own optimized parameters, reducing processing complexity while maintaining design flexibility.
Solution Approach 2:
Different regions of the integrated circuit are assigned different local characteristics: the first region has parameters optimized for FinFETs while the second region has parameters optimized for GAA transistors. This includes different gate lengths, dielectric thicknesses, and oxidation conditions tailored to each device type's specific requirements.
2Manufacturing precision
If separate regions with distinct parameters are used for different transistor types, then manufacturing precision and device performance are improved, but device layout complexity increases
Solution Approach 1:
The circuit layout is segmented into distinct first and second regions with clear boundaries, allowing each region to be designed and manufactured with optimized parameters for its specific transistor type, thereby improving manufacturing precision while organizing complexity into manageable sections.
Solution Approach 2:
The patent utilizes spatial separation in the layout by creating distinct regions at different locations on the substrate. This dimensional organization allows complex multi-parameter requirements to be satisfied through spatial arrangement rather than complicating the internal structure of each device region.
Data Source
AI summary
Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.