Multi-Gate Semiconductor Source/Drain Liners for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in improving device performance and reliability, particularly in multi-gate transistors with three-dimensional channels, where scaling and short channel effects are not adequately addressed.
Innovation Solution
The semiconductor device incorporates a multi-channel active pattern with a substrate and gate structures that include a combination of gate electrodes, gate insulating films, and gate spacers, utilizing materials like silicon and germanium, and employs negative capacitance FETs with ferroelectric and paraelectric material films to enhance current control and suppress short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-gate transistor with three-dimensional channel is used to increase device density, then device scaling is facilitated and short channel effects are suppressed, but device performance and reliability are not adequately improved
Solution Approach 1:
The patent introduces doped semiconductor liners with specific doping types (first dopant type at lower portion, second dopant type at upper portion) to create localized electrical characteristics in different regions of the source/drain structure. This local quality differentiation allows optimization of carrier concentration and mobility in specific areas to improve device performance while maintaining the 3D channel architecture for high density
Solution Approach 2:
The patent employs composite source/drain patterns consisting of multiple doped semiconductor liners (with different dopant types and concentrations) combined with semiconductor fill materials. This composite structure enables simultaneous achievement of high device density through 3D configuration and improved performance through tailored electrical properties in different layers
2Reliability
If gate structures are formed around the multi-channel active pattern to improve current control, then short channel effects are suppressed, but device complexity increases
Solution Approach 1:
The patent implements nested gate structures where gate electrodes are positioned at multiple levels (first gate electrode at lower level, second gate electrode at upper level) surrounding the multi-channel active pattern. This nested configuration provides enhanced current control and SCE suppression while organizing the complex gate structure in a hierarchical manner that manages fabrication complexity
3Reliability
If doped semiconductor liners are added to source/drain patterns to improve device performance, then current control is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the source/drain structure into distinct doped semiconductor liners at different vertical positions (lower and upper portions) with specific dopant assignments. This segmentation allows independent optimization of doping parameters for each region, making it easier to control and reproduce the desired electrical characteristics while managing manufacturing precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves device performance by facilitating scaling and reducing short channel effects, while maintaining effective current control, thereby enhancing the reliability and efficiency of the semiconductor device.
Implementation Method 1
employs negative capacitance FETs with ferroelectric and paraelectric material films to enhance current control
Implementation Method 2
negative capacitance FETs with ferroelectric and paraelectric material films
Data Source
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AI summary
A semiconductor device comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a plurality of gate structures disposed on the lower pattern to be spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films, source/drain recesses defined between adjacent gate structures and a source/drain pattern filling the source/drain recesses. Each source/drain pattern may include a first semiconductor liner, which extend along sidewalls and a bottom surface of the source/drain recesses, second semiconductor liners, which are on the first semiconductor liners and extend along the sidewalls and the bottom surface of the source/drain recesses, and a filling semiconductor film, which is on the second semiconductor liners and fills the source/drain recess. The second semiconductor liners may be doped with carbon, and the first semiconductor liners my be in contact with the lower pattern and the sheet patterns, while the first semiconductor liners may include carbonundoped regions.