Multi-gate Semiconductor Devices with Localized Channel Doping

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Solution Overview

Problem

Multi-gate semiconductor devices, such as FinFETs, with multiple voltage thresholds experience degraded performance and mobility due to high dopant concentrations in channel regions, which affect transistor performance and leakage current.

Innovation Solution

Optimizing the work function metal in multi-voltage threshold (VT) devices by selecting suitable gate electrode materials and channel doping concentrations to improve MOS transistor performance, while minimizing the impact on subsequent processing steps and maintaining low doping concentrations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high dopant concentrations are used in channel regions to achieve higher voltage thresholds, then voltage threshold control is improved, but transistor performance and mobility are degraded

Engineering Contradiction:
Improvevoltage threshold controlVSAvoidtransistor performance and mobility
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies local quality by implementing different dopant concentrations in different regions of the channel. Specifically, higher dopant concentrations are used in source/drain regions while lower concentrations are maintained in the channel region to preserve mobility. This spatial variation in dopant concentration allows simultaneous optimization of voltage threshold control and transistor performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs parameter changes by adjusting dopant concentration levels as a key parameter. By changing the dopant concentration from high in source/drain regions to low in channel regions, the patent achieves different electrical characteristics in different areas, resolving the contradiction between voltage threshold control and mobility.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If high dopant concentrations are used in channel regions to achieve higher voltage thresholds, then voltage threshold control is improved, but leakage current increases

Engineering Contradiction:
Improvevoltage threshold controlVSAvoidleakage current
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by implementing different dopant concentrations in different regions of the channel. Specifically, higher dopant concentrations are used in source/drain regions while lower concentrations are maintained in the channel region to preserve mobility. This spatial variation in dopant concentration allows simultaneous optimization of voltage threshold control and transistor performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs parameter changes by adjusting dopant concentration levels as a key parameter. By changing the dopant concentration from high in source/drain regions to low in channel regions, the patent achieves different electrical characteristics in different areas, resolving the contradiction between voltage threshold control and mobility.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8981479B2Multi-gate semiconductor devices and methods of forming the same
Publication Date: 2015.03.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8981479B2 patent drawing
  • US8981479B2 patent drawing
  • US8981479B2 patent drawing

AI summary

A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.