Multi-Gate Semiconductor Structure With Wet-Cleaned Nanosheet Channels
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Solution Overview
Problem
Existing methods for fabricating Gate-All-Around (GAA) transistor structures, such as nanosheet formation, often result in damage to sidewall and inner spacers, leading to leakage current and low reliability due to the consumption of these spacers during channel release operations.
Innovation Solution
A method involving a wet operation to clean exposed surfaces and trim nanosheet structures, mitigating damage to spacers and improving the reliability of multi-gate semiconductor structures by forming nanosheets within a gate trench, which includes a sacrificial gate structure and dielectric layer formation, followed by a wet cleaning and oxidation process to maintain spacer integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel release operations are performed to form nanosheet structures, then multi-gate transistor performance is improved, but sidewall and inner spacers are damaged leading to leakage currents
Solution Approach 1:
A sacrificial gate structure is formed over the fin structure before the channel release operation. This sacrificial gate protects the sidewall and inner spacers during the subsequent etching process that releases the nanosheet channel, preventing damage and leakage currents while still allowing the multi-gate transistor performance to be achieved.
2Ease of manufacture
If existing GAA FET fabrication methods are used, then nanosheet structures are formed, but spacer consumption occurs reducing device reliability
Solution Approach 1:
The sacrificial gate structure is formed in advance before the channel release etching step. This preliminary structure serves as a protective barrier that prevents the etchant from attacking and consuming the sidewall and inner spacers during the nanosheet formation process, thereby maintaining device reliability while enabling easy manufacture of GAA FET structures.
3Productivity
If aggressive etching is used to release channels, then fabrication productivity is improved, but spacer damage increases
Solution Approach 1:
The sacrificial gate structure is formed beforehand to provide protection during the channel release etching process. This allows the use of more aggressive etching conditions that improve fabrication productivity and speed, while the sacrificial gate prevents excessive spacer damage that would otherwise occur with such aggressive etching.
Solution Approach 2:
The sacrificial gate structure acts as an intermediary protective layer between the etchant and the sidewall/inner spacers. It absorbs the harsh etching conditions, allowing aggressive etching to proceed for high productivity while the intermediary protects the critical spacer structures from damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of multi-gate semiconductor structures by reducing spacer damage, thereby minimizing leakage current and improving electrical performance, while also increasing production efficiency and reducing costs through concurrent wet cleaning and oxidation processes.
Implementation Method 1
A wet operation is performed to clean exposed surfaces of the plurality of nanosheet structures
Implementation Method 2
A wet operation is performed to trim a thickness of each of the plurality of first semiconductor layers
Implementation Method 3
followed by a wet cleaning and oxidation process to maintain spacer integrity
Data Source
AI summary
A method for forming a multi-gate semiconductor structure is provided. A substrate including a fin structure is received. First portions of the fin structure are removed to expose a source/drain region of the fin structure. A semiconductor layer is formed in the source/drain region. Second portions of the fin structure are removed to expose a channel region of the fin structure. A surface of the channel region of the fin structure is cleaned. An interfacial layer is formed over the cleaned surface of the channel region of the fin structure.