Multi-Gate Nanosheet Structure With Stacked Source/Drain Regions
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Solution Overview
Problem
Existing semiconductor devices face challenges in integrating multi-gate transistors effectively while controlling current and suppressing short channel effects, particularly in scaling and channel potential interference.
Innovation Solution
A semiconductor device structure is designed with stacked lower and upper source/drain regions in a vertical direction, featuring buried contacts and specific gate electrode arrangements to enhance integration and current control, utilizing nanosheets and gate electrodes to optimize transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are used to increase integration density, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent implements a three-dimensional stacked nanosheet structure where multiple nanosheets are vertically stacked to form multi-gate transistors. This vertical stacking approach increases integration density by utilizing the third dimension (vertical direction) rather than only horizontal plane expansion, thereby resolving the contradiction between integration density and device complexity.
Solution Approach 2:
The transistor channel is segmented into multiple discrete nanosheets stacked vertically, with each nanosheet forming a separate gate-controlled channel. This segmentation allows independent control and optimization of each nanosheet while achieving high integration density through vertical stacking, addressing both integration density improvement and complexity management.
2Reliability
If gate length is increased to improve current control capability, then current control capability is improved, but device area increases
Solution Approach 1:
The patent enhances current control capability by stacking multiple nanosheets vertically to increase the effective channel width without increasing the horizontal gate length. The multi-gate structure wraps around the vertical channel, providing superior electrostatic control and current modulation while maintaining compact device footprint, thus resolving the contradiction between current control capability and device area.
3Device complexity
If conventional planar transistor structure is used, then device structure is simple, but short channel effect is not effectively suppressed
Solution Approach 1:
The patent transitions from planar two-dimensional channel structure to three-dimensional vertically stacked nanosheets with multi-gate wraparound configuration. This vertical stacking and multi-gate structure provides enhanced electrostatic control over the channel, effectively suppressing short channel effects such as drain-induced barrier lowering and threshold voltage roll-off, while maintaining reasonable structural complexity through systematic fabrication processes.
Solution Approach 2:
Multiple gate electrodes are merged into a unified multi-gate structure that surrounds the vertical nanosheet channel from multiple directions. This merging of gates provides comprehensive electrostatic control and effectively suppresses short channel effects by preventing potential interference from drain voltage, resolving the contradiction between structural simplicity and short channel effect suppression.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: lower nanosheets; upper nanosheets on the lower nanosheets; gate electrodes on the substrate and provided around each of the nanosheets; a first lower source/drain region on a first side of the first and second gate electrodes; a second lower source/drain region on a second side of the first and second gate electrodes; a first upper source/drain region on the first lower source/drain region; and a second upper source/drain region on the second lower source/drain region. A first length of the second lower source/drain region is greater than a second length of the second upper source/drain region.