Multi-Gate NVM Cell Dimension Control via Feedback
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Solution Overview
Problem
Variations in gate dimensions during the fabrication of multi-gate structures in semiconductor devices lead to reliability failures and performance degradation due to process tolerances and variations, affecting the program speed and yield of non-volatile memory systems.
Innovation Solution
The method involves adjusting subsequent gate formation steps based on measured dimensions of previously formed gate structures to control overall gate length and overlap, ensuring consistency across multi-gate structures by compensating for variations in select and control gates within split-gate NVM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-gate structures are formed using conventional processing steps, then the fabrication process is simple and fast, but gate dimension variations occur leading to reliability failures and performance degradation
Solution Approach 1:
The patent applies preliminary action by measuring the dimensions of first gates before forming second gates, and using these measurements to determine adjusted processing parameters for subsequent gate formation. This advance measurement and parameter adjustment ensures that overall gate length and overlap specifications are met despite variations in individual gate dimensions, thereby improving manufacturing precision without excessively complicating the overall process flow.
Solution Approach 2:
The patent implements feedback by measuring the actual dimensions of previously formed gates and using this measurement information to adjust processing parameters for subsequent gate formation steps. This closed-loop approach allows real-time compensation for process variations, ensuring consistent overall gate dimensions and reducing reliability failures while maintaining a manageable processing complexity through intelligent parameter adjustment.
2Productivity
If gate dimensions are not controlled, then the fabrication process is faster and simpler, but performance variations occur affecting program speed and yield
Solution Approach 1:
The patent applies self-service by having the process automatically measure gate dimensions and use this information to self-adjust subsequent processing parameters. The system serves itself by using its own measurement data to correct its own process variations, improving performance consistency without requiring external intervention or significantly slowing down the fabrication process.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting processing parameters for second gate formation based on measured dimensions of first gates. This adaptive parameter modification ensures that overall gate length and overlap specifications are maintained despite process variations, improving reliability and performance consistency while keeping the fabrication process efficient through intelligent parameter optimization rather than rigid process control.
Data Source
AI summary
Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).