Multi-Gate Non-Volatile Memory Cell Design
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Solution Overview
Problem
Multi-state non-volatile memory devices face challenges in achieving good data retention while maintaining cost-effectiveness due to the complexity and expense of fabricating multiple independent floating gates.
Innovation Solution
A thin-film storage multi-state non-volatile memory cell design with multiple gates spaced close together, overlapping inversion layers, and charge storage using nanocrystals or SONOS, eliminating the need for source/drain regions and reducing manufacturing complexity through a simplified process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple independent floating gates are used to achieve multi-state storage, then storage capacity increases, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent merges multiple floating gate functions into a single shared floating gate structure. Multiple control gates (first control gate, second control gate, third control gate) are positioned over different regions of the same charge storage layer, allowing independent charge injection into different portions of the shared floating gate. This eliminates the need for multiple independent floating gates while maintaining multi-state storage capability, directly resolving the contradiction between storage capacity and device complexity.
Solution Approach 2:
The patent segments the control mechanism into multiple independent control gates that can independently inject charge into different regions of the charge storage layer. Each control gate can be independently programmed to store charge in specific portions of the shared floating gate, creating multiple stable states. This segmentation of control functions while sharing the storage structure reduces device complexity while maintaining storage capacity.
2Quantity of substance
If multiple independent floating gates are used to achieve multi-state storage, then storage capacity increases, but manufacturing cost increases due to multiple masking steps
Solution Approach 1:
The patent combines multiple floating gate functions into a single continuous floating gate structure that shares a common formation process. The charge storage layer and floating gate are formed as unified structures, eliminating the need for separate masking and deposition steps for each floating gate. This merging approach maintains multi-state storage capability while significantly reducing manufacturing complexity and cost.
3Area of stationary object
If control gates are spaced close together to increase storage density, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating distinct functional regions within the charge storage layer through localized charge injection from different control gates. Each control gate region has specific charge distribution characteristics that can be independently controlled. This allows close spacing of control gates while maintaining distinct functional zones, achieving high area efficiency without excessive manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves significant storage capacity with good data retention and reduced manufacturing costs by simplifying the fabrication process and eliminating the need for multiple masking steps.
Implementation Method 1
Another type of non-volatile memory uses nanocrystals for charge storage
Implementation Method 2
One type of non-volatile memory uses traps in an insulating layer for charge storage. One material used in such a manner is silicon nitride. Typically, the nitride charge storage layer is surrounded by other insulating layers such as oxide forming an oxide-nitride-oxide (ONO) structure
Data Source
AI summary
A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.