Multigate Device External Resistance Mitigation via Selective Epitaxy

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Solution Overview

Problem

Multigate devices, such as finFET and tri-gate transistors, face limitations due to high external resistance (Rext) and interface state density (Dit) in III-V types, primarily due to challenges in forming high-quality contacts and a high concentration of interface states at the oxide/semiconductor interface.

Innovation Solution

A method involving the growth of two highly doped conformal epitaxial layers on the fins of multigate devices, followed by selective removal to form a trench, allowing for the formation of a gate within the trench, which reduces external resistance by maintaining doped epitaxial layers in source and drain regions while minimizing processing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication processes are used for III-V multigate devices, then device structure can be formed, but external resistance remains high due to difficulty in forming high-quality contacts

Engineering Contradiction:
Improvecontact qualityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by growing highly doped epitaxial layers in the source and drain regions before final contact formation. This pre-doping creates low-resistance regions that facilitate subsequent contact formation, addressing the contact quality issue while maintaining reasonable processing complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements local quality by creating highly doped regions specifically in the source and drain areas through selective epitaxial growth. This localized doping improves contact quality where needed without requiring global process changes, balancing reliability improvement with manufacturing ease

Inventive Principle:
Principle #3Local quality

2Reliability

If conventional fabrication processes are used for III-V multigate devices, then device structure can be formed, but interface state density remains high at the oxide/semiconductor interface

Engineering Contradiction:
Improveinterface state densityVSAvoidthermal budget constraints
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies parameter changes by modifying the doping concentration and distribution in the epitaxial layers. By creating highly doped regions adjacent to the oxide/semiconductor interface, the electrical properties are changed to reduce interface state effects without requiring high thermal budget processing

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses the highly doped epitaxial layer as an intermediary between the metal contact and the oxide/semiconductor interface. This intermediate layer mediates the interaction, reducing the impact of interface states on device performance while avoiding the need for high-temperature processing

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If highly doped epitaxial layers are grown and selectively removed to form trenches, then external resistance is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improveexternal resistanceVSAvoidfabrication process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the epitaxial layer formation into multiple highly doped layers with different doping concentrations and profiles. This segmented approach allows selective removal to form trenches while maintaining low external resistance, managing process complexity through structured segmentation

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach effectively lowers external resistance and interface state density, enhancing the performance of multigate devices by reducing contact resistance and improving high-speed device performance.

Implementation Method 1

growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9985113B2Fabrication process for mitigating external resistance of a multigate device
Publication Date: 2018.05.29 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9985113B2 patent drawing
  • US9985113B2 patent drawing
  • US9985113B2 patent drawing

AI summary

A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.