Multi-Gate Semiconductor Structure for Short-Channel Control
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Solution Overview
Problem
Multi-gate transistors face challenges in improving current control capability without increasing gate length and mitigating short channel effects, which affect the potential of the channel region due to drain voltage.
Innovation Solution
A semiconductor device design featuring a fin-shaped transistor with a gate electrode and source/drain pattern comprising a silicon-germanium semiconductor liner layer and filling layer, where the gate spacer includes an extension and protrusion portion, and a source/drain etching stop layer, enhancing control over the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length of the multi-gate transistor is increased to improve current control capability, then the current control capability is improved, but the device area increases and scaling becomes difficult
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional multi-gate structure (FinFET or nanowire) that wraps around the channel. This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sidewalls), achieving superior current control without increasing the lateral gate length, thus resolving the contradiction between current control capability and device area.
Solution Approach 2:
The gate structure is nested around the channel region, with the gate electrode surrounding the active pattern from multiple sides. This nested configuration maximizes the gate's control over the channel current while minimizing the footprint area, effectively addressing the contradiction between improved current control and reduced device area.
2Area of stationary object
If the gate length is reduced to enable scaling, then the device area decreases, but short channel effects increase due to drain voltage affecting channel potential
Solution Approach 1:
By adopting a three-dimensional multi-gate structure where the gate wraps around the channel, the patent achieves strong electrostatic control over the channel potential even with reduced gate length. The vertical and lateral gate fields suppress drain-induced barrier lowering and other short channel effects, enabling scaling while maintaining device performance.
Solution Approach 2:
The patent changes the geometric parameters of the gate structure from a simple planar configuration to a multi-dimensional wrapped configuration. This parameter change in gate geometry fundamentally alters the electric field distribution, providing enhanced control over channel potential and mitigating short channel effects even when the device is scaled down.
3Reliability
If a complex gate spacer structure with extension and protrusion portions is used to improve channel control, then the channel region control is enhanced, but the manufacturing complexity increases
Solution Approach 1:
The gate spacer is divided into functionally distinct segments: an extension portion that provides lateral spacing control and a protrusion portion that extends over the source/drain region. This segmentation allows each portion to perform its specific function independently, achieving superior channel control while maintaining manufacturing feasibility through modular structure formation.
Solution Approach 2:
The gate spacer exhibits local quality variations with different portions having different geometries and functions. The extension portion provides uniform spacing along the gate, while the protrusion portion provides localized coverage over the source/drain region. This local differentiation optimizes channel control in specific areas without requiring complex structures throughout the entire device.
Data Source
AI summary
There is provided a semiconductor device capable of improving performance and reliability of an element. The semiconductor device includes an active pattern extending in a first direction, and a plurality of gate structures spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode extending in a second direction and a gate spacer on a sidewall of the gate electrode and a source/drain pattern disposed between adjacent gate structures. The gate structure comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion protruding in a third direction beyond an upper surface of the active pattern. A maximum width of the upper portion of the semiconductor filling layer in the first direction is greater than a width of the semiconductor filling layer in the first direction on the upper surface of the active pattern. The semiconductor liner layer comprises an outer surface in contact with the active pattern and an inner surface facing the semiconductor filling layer. In a plan view, the inner surface of the semiconductor liner layer comprises a concave region.