Multi-Gate Source/Drain Contact Structure With Silicide Interface
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Solution Overview
Problem
Existing semiconductor devices face challenges in ensuring reliable electrical connections between source/drain contacts and source/drain regions, particularly in multi-gate transistors like MBCFETs, which can affect the integrity and performance of the device.
Innovation Solution
The semiconductor device incorporates a design with a first lower interlayer insulating layer, insulating patterns, gate electrodes, source/drain regions, and lower source/drain contacts, featuring a lower silicide layer and insulating liner layers to enhance the electrical connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are used to increase device density and improve current control, then device scaling and current control are improved, but reliability of electrical connection between source/drain contacts and source/drain regions deteriorates
Solution Approach 1:
A silicide layer is introduced as an intermediary between the source/drain contact and the source/drain region. This silicide layer improves electrical connectivity by providing a low-resistance interface, thereby resolving the reliability issue that arises from using multi-gate transistors for high-density integration.
Solution Approach 2:
The contact structure uses a composite material approach by combining the silicide layer with the source/drain region. This composite structure leverages the beneficial properties of both materials: the silicide provides low resistance for electrical connection, while the source/drain region maintains the transistor's switching functionality, thus solving the electrical connection reliability problem.
2Ease of operation
If gate length is increased to improve current control, then current control is improved, but device area increases
Solution Approach 1:
The patent transitions from planar current control to three-dimensional current control by implementing multi-gate structures (such as FinFET or nanosheet configurations). This dimensional change allows the gate to wrap around the channel in multiple directions, providing superior current control without increasing the lateral device footprint.
Solution Approach 2:
The multi-gate structure applies different functional qualities to different regions of the channel. The gate electrode is positioned to provide enhanced electric field control at critical locations along the channel, allowing effective current modulation with reduced overall device dimensions compared to uniform planar designs.
Data Source
AI summary
A semiconductor device includes a lower interlayer insulating layer, an insulating pattern extending in a first horizontal direction on a top surface of the lower interlayer insulating layer, first, second, and third gate electrodes extending in a second horizontal direction and arranged in the first horizontal direction, a first source/drain region between the first and second gate electrodes and a second source/drain region between the second and third gate electrodes on the insulating pattern, a lower source/drain contact extending into the second source/drain region by vertically penetrating the lower interlayer insulating layer and the insulating pattern, a top of the lower source/drain contact being higher than a top surface of the insulating pattern, a first insulating liner layer on both sidewalls of the lower source/drain contact, and a lower silicide layer between the second source/drain region and the lower source/drain contact.